STC3800 Datasheet, PDF(33/48 Page) Connor-Winfield Corporation – INTEGRATED

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STC3800 Datasheet, PDF (33/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

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Application Notes continued

Master/Slave Configuration â A pair of devices are interconnected by cross-coupling their respective Sync_8K or

Sync_Clk outputs to the other deviceâs Xref input (See Figure 10). Note that 8 kHz frame phase alignment is

maintained across a master/slave pair of devices only if Sync_8K is used as the cross couple signal.

Additionally, the reference inputs for each device would typically be correspondingly the same, so that when a Master/

Slave switch occurs, synchronization would continue with the same reference. The references may be driven by the

same signal directly or via separate drivers, as the redundancy of that part of the system requires. Distribution path

lengths are not critical here, as a phase build-out will occur when a device switches from slave to master.

The path lengths of the two Sync_8K or Sync_Clk to Xref signals is of interest, however. They need not be the same.

However, to accommodate path length delays, the STC3800 provides a programmable phase skew feature, which

allows the application to offset the output clocks from the cross-reference signal by up to Â± 32 ns, in 0.25nS increments.

This offset may therefore be programmed to exactly compensate for the actual path length delay associated with the

particular applicationâs cross-reference traces. The offset may further be adjusted to accommodate any output clock

distribution path delay differences. Phase offset is programmed by writing to the Phase_Offset register, and is typically

a one-time device initialization function. (See register description and Register Access Control sections). Thus,

master/slave switches with the STC3800 devices may be accomplished with near-zero phase hits.

For applications that use Hardware Control only (i.e. phase offset programming is not available), it is desirable to keep

the cross couple path lengths at a minimum and relatively equal in length, as the path length will appear as a phase hit

in the slave clock output when a master/slave switch occurs in a Hardware Control configuration.

Reference 1 In

Reference n In

Master / Slave Configuration

Figure 10

Ref1

STC3800

Sync_2K

RefSnTC3SB5yI0TnS0c__CCllkk

Sync_8K

Xref

2 kHz multi-frame sync

BITS clock output

Synchronized clock output

8 kHz

Xref

Ref1

Sync_8K

Sync_Clk

BITS_Clk