STC3800 Datasheet, PDF (22/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3E TIMING SOURCE

Register Descriptions and Operation continued
Intr_Event, 0x12 (R)
Bit 7
Bit 6
Loss of
Lock
Loss of
Signal
Bit 5
Active
reference
change
Bit 4
DPLL Mode
status
change
Bit 3
Xref Change
from no
activity to
activity
Bit 2
Xref Change
from activity
to no activity
Bit 1
Any reference
change
from not
available to
available
Bit 0
Any reference
change
from available
to not available
Interrupt state = 1. When an enabled interrupt occurs, the INTR pin is asserted, active low. All interrupts are cleared and the INTR
pin pulled high when the register is read. Reset default is 0.
Intr_Enable, 0x13 (R/W)
Bit 7
Bit 6
Enable Inter-
rupt event 7:
1: Enable
0: Disable
Default: 0
Enable Inter-
rupt event 6:
1: Enable
0: Disable
Default: 0
Bit 5
Enable Inter-
rupt event 5:
1: Enable
0: Disable
Default: 0
Bit 4
Bit 3
Enable Inter-
rupt event 4:
1: Enable
0: Disable
Default: 0
Enable Inter-
rupt event 3:
1: Enable
0: Disable
Default: 0
Bit 2
Enable Inter-
rupt event 2:
1: Enable
0: Disable
Default: 0
Bit 1
Enable Inter-
rupt event 1:
1: Enable
0: Disable
Default: 0
Bit 0
Enable Inter-
rupt event 0:
1: Enable
0: Disable
Default: 0
Enables or disables the corresponding interrupts from asserting the INTR pin. Interrupt events still appear in the Intr_Event register
independent of their “enable” state. Reset default is interrupts disabled.
Ref(1-8)_Frq_Offset, 0x14 ~ 0x1b (R)
Bit 7 ~ Bit 0
2’s complement value of frequency offset between reference and calibrated local oscillator, 0.2 ppm resolution
These registers indicate the frequency offset, in 0.2 ppm resolution, between each reference and the local calibrated freerun clock.
0x14 - 0x1b correspond to Ref1 - Ref8.
Preliminary Data Sheet #: TM061 Page 22 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice