FX828 Datasheet, PDF (4/34 Pages) CML Microcircuits – CTCSS/DCS/SELCALL Processor

CTCSS/DCS/SELCALL Processor
FX828
1.3 Signal List
Package
D2/D5/P4
Signal
Pin No.
Name
1
XTALN
2
XTAL/CLOCK
3
SERIAL CLOCK
4
COMMAND DATA
5
REPLY DATA
6
CSN
7
IRQN
Description
Type
O/P
I/P
I/P
I/P
O/P
I/P
O/P
The inverted output of the on-chip oscillator.
The input to the on-chip oscillator, for external
Xtal circuit or clock.
The "C-BUS" serial clock input. This clock,
produced by the µController, is used for transfer
timing of commands and data to and from the
device. See "C-BUS" Timing Diagram (Figure
4).
The "C-BUS" serial data input from the
µController. Data is loaded into this device in
8-bit bytes, MSB (B7) first, and LSB (B0) last,
synchronised to the SERIAL CLOCK. See
"C-BUS" Timing Diagram (Figure 4).
The "C-BUS" serial data output to the
µController. The transmission of REPLY DATA
bytes is synchronised to the SERIAL CLOCK
under the control of the CSN input. This 3-state
output is held at high impedance when not
sending data to the µController. See "C-BUS"
Timing Diagram (Figure 4).
The "C-BUS" data loading control function: this
input is provided by the µController. Data
transfer sequences are initiated, completed or
aborted by the CSN signal. See "C-BUS"
Timing Diagram (Figure 4).
This output indicates an interrupt condition to
the µController by going to a logic "0". This is a
"wire-ORable" output, enabling the connection of
up to 8 peripherals to 1 interrupt port on the
µController. This pin has a low impedance
pulldown to logic "0" when active and a high-
impedance when inactive. An external pullup
resistor is required.
The conditions that cause interrupts are
indicated in the IRQ FLAG register and are
effective if not masked out by a corresponding
bit in the IRQ MASK register.
© 2009 CML Microsystems Plc
4
D/828/4