FX828 Datasheet, PDF (21/34 Pages) CML Microcircuits – CTCSS/DCS/SELCALL Processor

CTCSS/DCS/SELCALL Processor
FX828
The Tx data is set in the DCS BYTE 3, DCS BYTE 2 and DCS BYTE 1 Registers ($85, $86 and $87).
Note that the DCS transmitter produces an inverted output. When the signal is fed through the summing
amp, in an inverting configuration, the correct polarity of the DCS signal will be restored (the modulator
gain blocks do not invert).
1.6.3 Receiver (CTCSS/Selcall Decoder)
The CTCSS/Selcall decoder should first be set up according to the desired characteristics. This entails
setting the TONE DECODER MODE Bit 2 of the SIGNALLING SET UP Register ($82), and setting the
TONE decoder bandwidth in the SIGNALLING SET-UP Register ($82), also programming the centre
frequencies of the desired tones in the RX TONE PROGRAM Register ($84). (It can hold up to 15
different tones). Any tone can be in any location. When the device is decoding, the tones are scanned in
the sequence of their location, i.e. $0 first and $E last. Once a tone is detected the remaining tones are
not checked. Therefore if two tones are close enough in frequency for their bandwidths to overlap then
the one in the lowest location will be detected.
The TONE IRQ MASK in the IRQ MASK Register ($8E) should also be set as required.
The TONE DECODER ENABLE in the SIGNALLING CONTROL Register ($80) should then be set to "1".
Whilst in the CTCSS/Selcall decoder mode the fast/predictive detector may be enabled (see below) (Bit 5
in the SIGNALLING CONTROL Register $80).
When the CTCSS/Selcall decoder detects a change in its present state an IRQ will be generated and Bit 3
of the IRQ FLAG Register ($8F) will indicate this. To reduce the likelihood of false or missed CTCSS
decodes, it is recommended that pre-emphasis and external audio pass-band filtering (300 to 3000Hz, for
example) be used in the Tx path.
The change that occurred can be read from Bit 4 of the SELCALL and SUB-AUDIO STATUS Register
($81) and if a tone is indicated by these bits then the number of that tone can be read from Bits 3, 2, 1
and 0 of the same register.
1.6.4 Receiver (CTCSS Fast/Predictive Detector)
This is used for detecting, in the fastest possible time, that sub-audio tones are present on the Rx
channel. Response time is optimised for speed at the expense of frequency resolution.
It can operate in parallel to the CTCSS/Selcall decoder. It is enabled using Bit 5 of the SIGNALLING
CONTROL Register ($80). It has an IRQ which may be unmasked with Bit 2 of the IRQ MASK Register
($8E). The FAST CTCSS MODE DETECT/PREDICTIVE Bit 3 in the SIGNALLING SET-UP Register
($82) allows for one of two alternatives in the FAST mode. In DETECT mode it will detect any periodic
tone in the sub-audio band and when in PREDICTIVE mode it will detect specific tones determined by the
frequency set in the CTCSS TX/FAST RX FREQUENCY Register ($83) and the fixed PREDICTIVE mode
bandwidth. Successful detection is indicated by the CTCSS FAST IRQ FLAG Bit 2 in the IRQ FLAG
Register ($8F), and the CTCSS FAST TONE Bit 6 in the SELCALL and SUB-AUDIO STATUS Register
($81).
1.6.5 Receiver (DCS Decoder)
The incoming signal is matched with the DCS code programmed into the DCS BYTE 1/2/3 Registers.
When the DCS decoder is enabled, the DCS DECODE/NO DECODE FLAG in Bit 7 of the SELCALL and
SUB-AUDIO STATUS Register ($81) will be set if the decode is successful (3 or fewer errors). A ''0" flag
indicates a failure to decode. This flag is updated for every bit of the incoming signal.
In order to detect the DCS turn-off code (134Hz), the CTCSS Tone Decoder should also be enabled and
programmed with this value. Once detected this will cause a CTCSS tone decode interrupt; the receiver
audio output should then be muted.
© 2009 CML Microsystems Plc
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