FX802 Datasheet, PDF (2/14 Pages) Sanyo Semicon Device – DC-DC Converter

Pin Number Function
FX802 FX802
J LG/LS
1
Row Address Strobe 2 (RAS2): Should be connected to the Row Address Strobe input of the second
1Mbit DRAM chip (if fitted).
2
1
Row Address Strobe 1 (RAS1): Should be connected to the Row Address Strobe input of the first
DRAM chip.
3
2
Write Enable (WE): The DRAM Read/Write control pin.
4
Xtal: The output of the on-chip clock oscillator. External components are required at this output when
a Xtal is employed. A Xtal cannot be used with the 24-pin version.
5
3
Xtal/Clock: The input to the on-chip clock oscillator inverter. A 4.0MHz Xtal or externally derived clock
should be connected here, see Figure 2. This clock provides timing for on-chip elements, filters etc. A
Xtal cannot be used with the 24-pin version. Various Xtal frequencies can be used with this device, see
Table 3 for the sampling clock rate variations.
6
4
Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the µController, by
going to a logic “0.” This is a “wire-or able” output, enabling the connection of up to 8 peripherals to 1
interrupt port on the µController. The pin has a low-impedance pulldown to logic “0” when active and a
high impedance when inactive.
Conditions indicated by this function are:
Power Reading Ready, Play Command Complete, Store Command Complete.
7
5
Serial Clock: The “C-BUS,” serial clock input. This clock, produced by the µController, is used for
transfer timing of commands and data to and from the DVSR Codec. See Timing Diagrams and
System Support Document, Document 2. The clock-rate requirements vary for differing FX802
functions.
8
6
Command Data: The “C-BUS,” serial data input from the µController. Data is loaded to this device in
8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams
and System Support Document, Document 2.
9
7
Chip Select (CS): The “C-BUS”, data transfer control function, this input is provided by the
µController. Command Data transfer sequences are initiated, completed or aborted by the CS signal.
See Timing Diagrams and System Support Document, Document 2.
10
8
Reply Data: The “C-BUS,” serial data output to the µController. The transmission of Reply Data bytes
is synchronized to the Serial Data Clock under the control of the Chip Select input. This 3-state output
is held at high impedance when not sending data to the µController. See Timing Diagrams and System
Support Document, Document 2.
11
9
12
10
V_BIAS: The output of the on-chip analogue circuitry bias system, held internally at V_DD/2. This pin should
be decoupled to V by a capacitor C , See Figure 2.
SS
1
Audio Out: The analogue signal output.
13
11
Audio In: The audio (speech) input. The signal to this pin must be a.c. coupled by a capacitor C and
4
decoupled to V_SS by an HF bypass capacitor C₆. For optimum noise performance this input should be
driven from a source impedance of less than 100Ω.
14
12
V_SS: Negative supply rail (GND).
2