FX802 Datasheet, PDF (1/14 Pages) Sanyo Semicon Device – DC-DC Converter

FX802
DVSR CODEC
SERIAL
CLOCK
DATA
READ
COUNTER
COMMAND
REPLY
DATA
DATA
CS
XTAL/
IRQ
CLOCK XTAL
C-BUS INTERFACE AND CONTROL LOGIC
CLOCK
GENERATOR
DATA
WRITE
COUNTER
PLAY
COMMAND
BUFFER
STORE
COMMAND
BUFFER
SPEECH
PLAY
COUNTERS
SPEECH
STORE
COUNTERS
CONTROL
REGISTER
STATUS
REGISTER
ENCODER
CLOCK
POWER
ASSESS
DECODER
CLOCK
ENCODE
CLOCK
AUDIO
IN
AUDIO
BYPASS
AUDIO
OUT
VBIAS
DECODER
OUTPUT
MOD
DECODE
CLOCK
IDLE
PATTERN
DEMOD
DRAM CONTROL AND TIMING
DIRECT ACCESS CLOCKS and DATA
WE CAS RAS 1 RAS 2 RAS 3 RAS 4
A9 A8
A7 A6
A5 A4 A3/ECK _A2/DCK
DRAM ADDRESS LINES
A0/ENO
(ENCODER
OUT)
A1/ DEI
(DECODER
IN)
VDD
VBIAS
VSS
Fig.1 FX802 DVSR Codec
Brief Description
The FX802 DVSR Codec contains:
A Continuously Variable Slope Delta Modulation (CVSD)
encoder and decoder.
Control and timing circuitry for up to 4Mbits of external
Dynamic Random Access Memory (DRAM).
“C-BUS” µProcessor interface and control logic.
When used with external DRAM, the FX802 has four primary
functions:
q Speech Storage
Speech signals present at the Audio Input may be digitized
by the CVSD encoder, and the resulting bit stream stored
in DRAM. This process also provides readings of input
power level for use by the system µController.
q Speech Playback
Previously digitized speech data may be read from DRAM
and converted back into analogue form by the CVSD
decoder.
q Data Storage
Digital data sent over the “C-BUS” from the system
µController may be stored in DRAM.
q Data Retrieval
Digital data may be read from DRAM and sent over
“C-BUS” to the system µController.
Speech storage and playback may be performed
concurrently with data storage or retrieval.
Publication D/802/4 December 1995
The FX802 may also be used without DRAM (as a “stand-
alone” CVSD Codec), in which case direct access is
provided to the CVSD Codec digital data and clock signals.
All functions are controlled by “C-BUS” commands from
the system µController.
The Storage, Recovery and Replay functions of the
FX802 can be used for:
q Answering Machine applications, where an incoming
speech message is stored for later recall.
q Busy Buffering, an outgoing speech message is stored
temporarily until the transmit channel becomes free.
q Automatic transmission of pre-recorded ‘Alarm’ or
status announcements.
q Time Domain Scrambling of speech messages.
q VOX control of transmitter functions.
q Temporary Data Storage applications, such as
buffering of over-air data transmissions.
On-chip the Delta Codec is supported by input and output
analogue switched-capacitor filters and audio output
switching circuitry. The DRAM control and timing circuitry
provides all the necessary address, control and refresh
signals to interface to external DRAM.
The FX802 DVSR Codec is a low-power 5-volt CMOS LSI
device.