FX802 Datasheet, PDF (10/14 Pages) Sanyo Semicon Device – DC-DC Converter

“Read Status Register” – Address/Command, 61 , followed by 1 byte of Reply Data.
H
Reading
Function
MSB
Bit 7
1
6
1
5
1
43 2 1 0
00 0 0 0
00 0 0 1
00 0 1 0
00 0 1 1
00 1 0 0
00 1 0 1
00 1 1 0
00 1 1 1
01 0 0 0
01 0 0 1
01 0 1 0
01 0 1 1
01 1 0 0
01 1 0 1
01 1 1 0
01 1 1 1
10 0 0 0
10 0 0 1
10 0 1 0
10 0 1 1
10 1 0 0
10 1 0 1
10 1 1 0
10 1 1 1
11 0 0 0
11 0 0 1
11 0 1 0
11 0 1 1
11 1 0 0
11 1 0 1
11 1 1 0
11 1 1 1
Power Reading
Ready
Store Command
Complete
Play Command
Complete
Power Register
Pwr Compand Bits/page
0
1
2
3
4
5
6
7
-39.0 dB
8
10
-36.0
12
14
-33.5
16
18
-30.0
20
22
-28.0
24
32
-25.0
40
48
-22.0
56
64
-19.0
72
80
-16.0
88
128
-10.0
192
256
-6.0
320
384
0dB
448
512
Table 6 Status Register
Interrupts
An Interrupt Request (IRQ), (if enabled by the Control
Register) is produced by the FX802 to report the following
actions:
Power Reading Ready
Store Command Complete
Play Command Complete.
When an Interrupt Request is produced the Status Register
must be read to ascertain the source of the interrupt. This
action will clear the IRQ output.
Store Command Complete bit
(and an interrupt) is set on completion of a Store command.
This bit is cleared by loading the next Store command, or by
a General Reset command (01_H).
Play Command Complete bit
(and an interrupt) is set on completion of a Play command.
This bit is cleared by loading the next Play command, or by a
General Reset command (01 ).
H
Power Reading Ready bit
(and an interrupt) is set for every 1024 (1 page) voice-data
bits from the Encoder. This bit is cleared after reading the
Status Register, or by a General Reset command (01 ).
H
Power Register
The power assessment element shown in Figure 1 assesses
the input signal power for each encoded ‘page’ (every 1024
encoder output bits) by counting the number of 'compand
bits' (000 or 111 sequences in the output bit-stream)
produced during that ‘page,’ shown in Table 6, with typical
encoder input power levels (dB).
Power Reading measurements (Bits 0 – 4) are produced
under the same conditions as in Figure 4.
At the end of each ‘page’ the “Power Reading Ready” bit of
the Status Register is set, an Interrupt Request is generated
(if enabled) and the resulting count converted to a 5-bit
quasi-logarithmic form.
The Power Register reading is interpreted as below.
00000 represents
00001 represents
11111 represents
0 compand bits
1 compand bit
512 compand bits
– the maximum.
This “Power” reading is placed in the Status Register
where it can be read by the µC.
Figure 4 shows this output in graphical form, indicating the
typical Input Power Level.
5-Bit Power Reading
30 ^{(Status Register – bits 0 to 4)}
20
10
0
-50
-40
-30
Fig.4 Typical “Power” Readings vs Input Level
Input Frequency = 1.0kHz
Sample Clock Rate = 32kb/s
0dB Ref:
= 308mVrms
-20
10
308mVrms
-10
0dB
5.0
Average Input ‘Power Level’ (dB )