CPC7594 Datasheet, PDF (17/20 Pages) Clare, Inc. – Line Card Access Switch

In order for the SCR to crowbar (or foldback), the
SCR’s on-voltage (see “Protection Circuitry Electrical
Specifications” on page 10) must be less than the
applied voltage at the V_BAT pin. If the V_BAT voltage is
less negative than the SCR on-voltage or if the V_BAT
supply is unable to source the trigger current, the SCR
will not crowbar.
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to a diode
drop above ground and the fault current directed to
ground. The negative cycle of the transient will cause
the SCR to conduct when the voltage exceeds the
V_BAT reference voltage by two to four volts, steering
the fault current to ground.
Note: The CPC7594xB does not contain the
protection SCR but instead uses diodes to clamp both
polarities of a transient fault. These diodes direct the
negative potential’s fault current to the V_BAT pin.
2.9.2 Current Limiting function
If a lightning strike transient occurs when the device is
in the talk state, the current is passed along the line to
the integrated protection circuitry and restricted by the
dynamic current limit response of the active switches.
During the talk state, when a 1000V 10x1000 μs
lightning pulse (GR-1089-CORE) is applied to the line
though a properly clamped external protector, the
current seen at T_LINE and R_LINE will be a pulse with a
typical magnitude of 2.5 A and a duration less than
0.5 μs.
If a power-cross fault occurs with the device in the talk
state, the current is passed though break switches
SW1 and SW2 on to the integrated protection circuit
but is limited by the dynamic DC current limit response
of the two break switches. The DC current limit
specified over temperature is between 80 mA and
425 mA and the circuitry has a negative temperature
coefficient. As a result, if the device is subjected to
extended heating due to a power cross fault condition,
the measured current at T_LINE and R_LINE will decrease
as the device temperature increases. If the device
temperature rises sufficiently, the temperature
shutdown mechanism will activate and the device will
enter the all-off state.
CPC7594
2.10 Thermal Shutdown
The thermal shutdown mechanism activates when the
device die temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown events the T_SD
pin will output a logic low with a nominal 0 V level. A
logic high is output from the T_SD pin during normal
operation with a typical output level equal to V_DD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown mechanism will activate forcing the switches
to the all-off state. At this point the current measured
into T_LINE or R_LINE will drop to zero. Once the device
enters thermal shutdown it will remain in the all-off
state until the temperature of the device drops below
the de-activation level of the thermal shutdown circuit.
This permits the device to autonomously return to
normal operation. If the transient has not passed,
current will again flow up to the value allowed by the
dynamic DC current limiting of the switches and
heating will resume, reactivating the thermal shutdown
mechanism. This cycle of entering and exiting the
thermal shutdown mode will continue as long as the
fault condition persists. If the magnitude of the fault
condition is great enough, the external secondary
protector will activate shunting the fault current to
ground.
2.11 External Protection Elements
The CPC7594 requires only over voltage secondary
protection on the loop side of the device. The
integrated protection feature described above negates
the need for additional external protection on the SLIC
side. The secondary protector must limit voltage
transients to levels that do not exceed the breakdown
voltage or input-output isolation barrier of the
CPC7594. A foldback or crowbar type protector is
recommended to minimize stresses on the CPC7594.
Consult Clare’s application note, AN-100, “Designing
Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces” for equations related
to the specifications of external secondary protectors,
fused resistors and PTCs.
R03
www.clare.com
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