CPC7594 Datasheet, PDF (12/20 Pages) Clare, Inc. – Line Card Access Switch

CPC7594
2. Functional Description
2.1 Introduction
2.1.1 CPC7594xA and CPC7594xB Logic States
• Talk. Break switches SW1 and SW2 closed, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
• Ringing. Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 open.
• Test. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and channel test
switches SW5 and SW6 closed.
• All-off. Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
2.1.2 CPC7594xC Logic States
The CPC7594xC replaces the Test state with the
Test/Monitor state as defined below.
• Test/Monitor. Break switches SW1 and SW2
closed, ringing switches SW3 and SW4 open, and
test switches SW5 and SW6 closed.
The CPC7594 offers break-before-make and
make-before-break switching from the ringing state to
the talk state with simple TTL level logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ring
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State control is via TTL
logic-level input so no additional driver circuitry is
required. The linear break switches SW1 and SW2
have exceptionally low R_ON and excellent matching
characteristics. The ringing switch, SW4, has a
minimum open contact breakdown voltage of 465 V at
+25°C sufficiently high with proper protection to
prevent breakdown in the presence of a transient fault
condition (i.e., passing the transient on to the ringing
generator).
Integrated into the CPC7594 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection for the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
away from the SLIC via the protection diode bridge or
the optional integrated protection SCR. Power-cross
potentials are also reduced by the current limiting and
thermal shutdown circuits.
To protect the CPC7594 from an over-voltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the tip and ring terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC7594
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
The CPC7594 operates from a single +5 V supply.
This gives the device extremely low power
consumption in any state with virtually any range of
battery voltage. The battery voltage used by the
CPC7594 has a two fold function. It is used as a
reference and as a current source for the internal
integrated protection circuitry under surge conditions.
Second, it is used as a reference. In the event of
battery voltage loss, the CPC7594 enters the all-off
state.
2.2 Under Voltage Switch Lock Out Circuitry
2.2.1 Introduction
Smart logic in the CPC7594 now provides for switch
state control during both power up and power loss
transitions. An internal detector is used to evaluate the
V_DD supply to determine when to de-assert the under
voltage switch lock out circuitry with a rising V_DD and
when to assert the under voltage switch lock out
circuitry with a falling V_DD. Any time unsatisfactory low
V_DD conditions exist the lock out circuit overrides user
switch control by blocking the information at the
external input pins and conditioning internal switch
commands to the all off state. Upon restoration of V_DD
the switches will remain in the all-off state until the
LATCH input is pulled low.
The rising V_DD lock out release threshold is internally
set to ensure all internal logic is properly biased and
functional before accepting external switch commands
from the inputs to control the switch states. For a
falling V_DD event, the lock out threshold is set to
assure proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed.
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