CPC7594 Datasheet, PDF (15/20 Pages) Clare, Inc. – Line Card Access Switch

CPC7594
1. Pull T_SD to a logic low to end the ringing state.
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
2. Keep T_SD low for at least one-half the duration of
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break-before-make state.
3. During the T_SD low period, set the IN_RINGING and
IN_TEST inputs to the talk state (0, 0).
4. Release T_SD, allowing the internal pull-up to
activate the break switches.
When using T_SD as an input, the two recommended
states are “0” which overrides the logic input pins and
forces an all off state and “Z” which allows normal
switch control via the logic input pins. This requires the
use of an open-collector or open-drain type buffer.
Forcing T_SD to a logic high prevents the user from
detecting a thermal shutdown condition and is
therefore not recommended.
Alternate Break-Before-Make Ringing to Talk Transition Logic Sequence
State IN_RINGING IN_TEST LATCH T_SD
Timing
Ringing
Break Return
Switches Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing
1
0
0
Z
-
Off
On
On
Off
All-Off
1
Break-
Before-
0
Make
Talk
0
Hold this state for at least one-half of the
0
ringing cycle. SW4 waiting for zero
Off
Off
On
Off
X
0
current to turn off.
0
SW4 has opened
Off
Off
Off
Off
0
0
Z
Close Break Switches
On
Off
Off
Off
2.4 Data Latch
The CPC7594 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch is via the input pins IN_RINGING and IN_TEST while
the output of the data latch are internal nodes used for
state control. When the LATCH enable control pin is at
a logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch state.
Whenever the LATCH enable control pin is at logic 1,
the data latch is active and data is locked. Subsequent
changes to the input controls IN_RINGING and IN_TEST
will not result in a change to the control logic or affect
the existing switch state.
The switches will remain in the state they were in
when the LATCH changes from logic 0 to logic 1 and
will not respond to changes in input as long as the
LATCH is at logic 1. However, neither the T_SD input
nor the T_SD output control functions are affected by
the latch function. Since internal thermal shutdown
control and external “All-off” control is not affected by
the state of the LATCH enable input, T_SD will override
state control.
2.5 T_SD Pin Description
The T_SD pin is a bi-directional I/O structure with an
internal pull-up current source having a nominal value
of 16 μA biased from V_DD.
As an output, this pin indicates the status of the
thermal shutdown circuitry. Typically, during normal
operation, this pin will be pulled up to V_DD but under
fault conditions that create excess thermal loading the
CPC7594 will enter thermal shutdown and a logic low
will be output.
R03
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