CPC7508 Datasheet, PDF (11/14 Pages) Clare, Inc. – Line Card Access Switch

CPC7508
There are six possible start up scenarios that can
occur during power up. They are:
1. All inputs defined at power up & LATCH = 0
2. All inputs defined at power up & LATCH = 1
3. All inputs defined at power up & LATCH = Z
4. All inputs not defined at power up & LATCH = 0
5. All inputs not defined at power up & LATCH = 1
6. All inputs not defined at power up & LATCH = Z
Under all of the start up situations listed above the
CPC7508 will hold all of it’s switches in the all-off state
during power up. When V_DD requirements have been
satisfied the LCAS will complete it’s start up procedure
in one of three conditions.
For start up scenario 1 the CPC7508 will transition
from the all-off state to the state defined by the inputs
when V_DD is valid.
For start up scenarios 2, 3, 5, and 6 the CPC7508 will
power up in the all-off state and remain there until the
LATCH pin is pulled low. This allows for an indefinite
all-off state for boards inserted into a powered system
but are not configured for service or boards that need
to wait for other devices to be configured first.
Start up scenario 4 will start up with all switches in the
all-off state but upon the acceptance of a valid V_DD the
LCAS will revert to one of the legitimate states listed in
the truth tables and there after may randomly change
states based on input pin leakage currents and
loading. Because the LCAS state after power up can
not be predicted with this start up condition it should
never be utilized.
On designs that do not wish to individually control the
LATCH pins of multi-port cards it is possible to bus
many (or all) of the LATCH pins together to create a
single board level input enable control.
2.3.2.3 Power Loss Sequence
For a falling V_DD event, the under voltage lock out
detector monitors the supply voltage and upon
reaching the internally set threshold point asserts the
under voltage lock out command. This feature protects
the integrity of the application during power dropouts
by assuring proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed. Upon assertion of the under
voltage lock out command the switch control logic is
conditioned into the All_Off state where it will remain
until V_DD recovers and the LATCH input is pulled low.
2.3.3 Data Latch
The CPC7508 has an integrated transparent data
latch controlled by the LATCH input which can be used
as an enable or a chip select function when the INx
inputs of multiple LCAS devices are connected to
common busses. The latch enable operation is
controlled by TTL input logic levels at the LATCH pin.
Control data is input to the latch via the input pins IN_A,
IN_B and IN_C while the output of the data latch are
internal nodes used for state control. When the
LATCH enable input control pin is a logic 0 (low) the
data latch is transparent and any change to the inputs
will flow directly through the latch to the state control
circuitry and be reflected by a change in the switches
status.
Whenever the LATCH enable control pin is at logic 1,
the data latch is active and data is locked. Subsequent
changes to the input controls IN_A, IN_B and IN_C will not
result in a change to the control logic or affect the
existing switch state.
2.4 T_SD Pin Description
The T_SD pin is a bi-directional I/O structure used as an
output to indicate a thermal shutdown event is in effect
and as an input to condition the device into the All-Off
state.
As an output, this pin indicates the status of the
thermal shutdown circuitry. During normal operation
the output will be pulled up to a logic high by an
external resistor tied to the local logic supply voltage.
Under a line fault situation that creates excess thermal
loading, the CPC7508 will enter thermal shutdown
and a logic low will be output.
As an input, the T_SD pin is utilized to place the
CPC7508 into the “All-Off” state by simply pulling the
input to a logic low. Clare recommends the use of an
open-collector or an open-drain type output from the
control logic to manage the All-Off state using the T_SD
pin.
Forcing T_SD to a logic 1 or tying this pin to V_CC will not
prevent normal operation of the thermal shutdown
circuitry inside the CPC7508. It will however prevent
the user from detecting a thermal shutdown condition
and is therefore not recommended.
R04
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