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CPC7508 Datasheet, PDF (10/14 Pages) Clare, Inc. – Line Card Access Switch
CPC7508
means to test the drop without the loading effects of
the line feed circuitry.
• Test_IN Monitor. Break switches SW1 and SW2
plus the TEST_IN switches SW5 and SW6 closed,
all other switches open. With this state it is possible
to monitor the SLIC output while the SLIC is driving
the line.
• Test_OUT Monitor. Break switches SW1 and SW2
plus the TEST_OUT switches SW3 and SW4
closed, all other switches open. With this state it is
possible to monitor the LCAS output while the SLIC
is driving the line.
• Test_IN & OUT. TEST_IN switches SW5 and SW6
plus the TEST_OUT switches SW3 and SW4
closed, all other switches open. This state allows
simultaneous testing of the transmission channel
and the drop.
• Test_IN BRIDGE. TEST_IN switches SW5 and
SW6 plus TEST BRIDGE switches SW7 and SW8
closed, all other switches open. This state allows
connecting the SLIC output to the Test Out bus to
compare the on-hook TEST_OUT Monitor
evaluation. This makes it possible to determine if
there is a failure with the Break Switches.
• All-Off. All switches open. Activation of this state can
be accomplished by setting the appropriate INX
pattern or by pulling the TSD input/output low.
2.3 Switch Logic and Control
2.3.1 Introduction
The CPC7508 uses a three input transparent latch as
the interface between the externally controlled inputs,
INA, INB and INC and the switch logic. Control of the
transparent latch is by means of the LATCH input.
Data output from the latch is fed into the switch control
logic which decodes the inputs and drives the
appropriate switches. To prevent undesirable switch
activity during both start-up and power down the
switch control logic also contains under voltage lock
out detection circuitry to manage the behavior of the
CPC7508. The under voltage lock out release
threshold is internally set to ensure all internal logic is
properly biased before accepting external switch
commands from the INx inputs to control the switch
states. Prior to release of the under voltage lock out,
the switch control logic is conditioned to the All-Off
state
2.3.2 Under Voltage Detection and Switch Lock Out
Under voltage detection circuitry in the CPC7508
consists of an internal detector to evaluate the VDD
supply and smart logic to provide for switch state
control during both power up and power loss
transitions.
Any time an unsatisfactory condition causes the VDD
supply to fall below the internally set under voltage
lockout threshold, the smart logic overrides user
switch control by blocking the information at the INx
input pins and conditions the switch control logic to
place the switches into the All-Off state.
2.3.2.1 Power Up Sequence
Upon power up, the under voltage detector and smart
logic become active before the switch driver circuits
and the switch control logic can activate any of the
switches. As the VDD supply starts up, the rising
supply voltage is evaluated by the under voltage
detector to determine when to de-assert the under
voltage switch lock out command. Prior to release of
the lock out command, the smart logic preconditions
the switch control logic for the All-Off state.
The All_Off state is sustained by holding the LATCH
input at a logic high level. This is accomplished by an
external resistor at the LATCH pin which pulls the
input to the supply voltage used by the on-board logic.
The LATCH logic high secures the switch control logic
and the CPC7508 remains in the All-Off state until the
LATCH input is pulled down to a logic low. Prior to the
assertion of a logic low at the LATCH pin, the control
inputs INA, INB and INC must be properly conditioned.
2.3.2.2 Hot Plug and Power Up Circuit Design
Considerations
To facilitate hot plug insertion and power up control the
LATCH pin has an external pull up resistor to the local
logic power rail that will hold a non-driven LATCH pin
at a logic high state. This enables board designers to
use the CPC7508 with FPGAs and other devices that
provide high impedance outputs during power up and
configuration.
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