WM8944B Datasheet, PDF (93/165 Pages) Cirrus Logic – Mono Low-Power CODEC with Video Buffer

SCLK
SDA
D7
D1 R/W
A15
A9 A8
START
device ID (Write) ACK register address A15 – A8
A7
A1 A0
D7
register address A7 – A0 ACK
Rpt
START
device ID
WM8944B
D1 R/W
B15
B9 B8
B7
B1 B0
device ID
(Read) ACK
data bits B15 – B8
ACK
data bits B15 – B8
ACK
STOP
Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses
Figure 35 Control Interface 2-wire (I2C) Register Read
The Control Interface also supports other register operations, as listed above. The interface protocol
for these operations is summarised below. The terminology used in the following figures is detailed in
Table 66.
Note that, for multiple write and multiple read operations, the auto-increment option must be enabled.
This feature is enabled by default, as noted in Table 65.
TERMINOLOGY
DESCRIPTION
S
Start Condition
Sr
Repeated start
A
Acknowledge (SDA Low)
¯A¯
Not Acknowledge (SDA High)
P
Stop Condition
R/¯W¯
ReadNotWrite
0 = Write
1 = Read
[White field]
Data flow from bus master to WM8944B
[Grey field]
Data flow from WM8944B to bus master
Table 66 Control Interface Terminology
8 bit Device ID
8 bits
8 bits
8 bits
8 bits
S
Device ID RW A MSByte Address A LSByte Address A
MSByte Data
A
LSByte Data
AP
(0)
Figure 36 Single Register Write to Specified Address
S
Device ID RW A MSByte Address A LSByte Address A Sr
(0)
Figure 37 Single Register Read from Specified Address
Device ID RW A
MSByte Data
A
LSByte Data
AP
(1)
Rev 4.3
93