WM8944B Datasheet, PDF (38/165 Pages) Cirrus Logic – Mono Low-Power CODEC with Video Buffer

WM8944B
The SE2 ‘enable’ bits are described in Table 14. Note that (with the exception of the SE2 HPF) other
control fields must also be determined and written to the WM8944B using WISCE™ or other tools.
The registers described below only allow the sub-blocks of SE2 to be enabled or disabled.
Note that it is not recommended to access these control fields unless appropriate values have been
written to the associated bits in registers R99 to R175.
REGISTER
ADDRESS
R99 (63h)
SE2_HPF_CO
NFIG
BIT
LABEL
1
SE2_HPF_R_E
NA
0
SE2_HPF_L_EN
A
R100 (64h)
1
SE2_RETUNE_
SE2_RETUNE
R_ENA
_CONFIG
0
SE2_RETUNE_
L_ENA
R133 (85h)
0
SE2_5BEQ_L_E
SE2_5BEQ_C
NA
ONFIG
Table 14 Signal Enhancement Block 2 (SE2)
DEFAULT
0
0
0
0
0
DESCRIPTION
SE2 Right channel High-pass filter
enable
0 = Disabled
1 = Enabled
SE2 Left channel High-pass filter
enable
0 = Disabled
1 = Enabled
SE2 Right channel ReTune filter
enable
0 = Disabled
1 = Enabled
SE2 Left channel ReTune filter
enable
0 = Disabled
1 = Enabled
SE2 Left channel 5-band EQ enable
0 = Disabled
1 = Enabled
The register controls for Signal Enhancement Block SE3 are defined in the “Dynamic Range Control
(DRC)” section.
DYNAMIC RANGE CONTROL (DRC)
The dynamic range controller (DRC) is a circuit which can be enabled in the digital playback or digital
record path of the WM8944B, depending upon the selected DSP mode. The function of the DRC is to
adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range,
e.g. when recording from microphones built into a handheld system.
The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anti-
clip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the
presence of loud impulsive noises.
The DRC also incorporates a Noise Gate function, which provides additional attenuation of very low-
level input signals. This means that the signal path is quiet when no signal is present, giving an
improvement in background noise level under these conditions.
The DRC is enabled as described in Table 15. The audio signal path controlled by the DRC depends
upon the selected DSP Configuration mode - see “DSP Core” for details.
If the DRC is used in the record path then to remove any DC offset from the input signal the ADC high
pass filter must be enabled. The ADC HPF is enabled when ADC_HPF = 1. This is the default
condition. The DRC will not function correctly if there is any DC offset..
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