WM8944B Datasheet, PDF (109/165 Pages) Cirrus Logic – Mono Low-Power CODEC with Video Buffer

REGISTER BIT
ADDRESS
LABEL
Register 03h Power management 2
WM8944B
DEFAULT
DESCRIPTION
REFER TO
DAC_ENA must be set to 1 when processing data from the
DAC or Digital Beep Generator.
REGISTER
ADDRESS
R4 (04h)
Audio
Interface
BIT
15:14
13:12
11:10
9
8
6
5
4
LABEL
DEFAULT
DESCRIPTION
DACDATA_
PULL [1:0]
FRAME_PULL
[1:0]
BCLK_PULL
[1:0]
ADCR_SRC
ADCL_SRC
DAC_SRC
BCLK_INV
LRCLK_INV
00
DACDAT pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
10 = pull-up
11 = reserved
00
LRCLK pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
10 = pull-up
11 = reserved
00
BCLK pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
10 = pull-up
11 = reserved
1
Right Digital Audio interface source
0 = Left ADC data is output on right channel
1 = Right ADC data is output on right channel
0
Left Digital Audio interface source
0 = Left ADC data is output on left channel
1 = Right ADC data is output on left channel
0
DAC Data Source Select
0 = DAC outputs left channel interface data
1 = DAC outputs right channel interface data
0
BCLK Invert
0 = BCLK not inverted
1 = BCLK inverted
0
LRCLK Polarity / DSP Mode A-B select.
REFER TO
Left and I2S modes – LRCLK polarity
0 = Not Inverted
1 = Inverted
Rev 4.3
3:2
WL [1:0]
1:0
FMT [1:0]
DSP Mode – Mode A-B select
0 = MSB is available on 2nd BCLK rising edge after LRCLK
rising edge (mode A)
1 = MSB is available on 1st BCLK rising edge after LRCLK
rising edge (mode B)
10
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
Note - see “Companding” for the selection of 8-bit mode.
10
Digital Audio Interface Format
00 = Reserved
109