WM8944B Datasheet, PDF (53/165 Pages) Cirrus Logic – Mono Low-Power CODEC with Video Buffer

Rev 4.3
WM8944B
OUTPUT SIGNAL PATHS ENABLE
Each analogue output pin can be independently enabled or disabled using the register bits described
in Table 31. The speaker PGA and mixers can also be controlled.
REGISTER
ADDRESS
R3 (03h)
Power
management
2
BIT
LABEL
14 OUT_ENA
12 SPK_PGA_ENA
11 SPKN_SPKVDD_
ENA
10 SPKP_SPKVDD_
ENA
7 SPKN_OP_ENA
6 SPKP_OP_ENA
2 SPK_MIX_ENA
Table 31 Output Signal Paths Enable
DEFAULT
DESCRIPTION
0
LINEOUT enable
0 = Disabled
1 = Enabled
0
Speaker PGA enable
0 = Disabled
1 = Enabled
0
SPKOUTN enable
0 = Disabled
1 = Enabled
Note that SPKOUTN is also
controlled by SPKN_OP_ENA.
When powering down SPKOUTN,
the SPKN_SPKVDD_ENA bit
should be reset first.
0
SPKOUTP enable
0 = Disabled
1 = Enabled
Note that SPKOUTP is also
controlled by SPKP_OP_ENA.
When powering down SPKOUTP,
the SPKP_SPKVDD_ENA bit
should be reset first
0
SPKOUTN enable
0 = Disabled
1 = Enabled
Note that SPKOUTN is also
controlled by
SPKN_SPKVDD_ENA. When
powering up SPKOUTN, the
SPKN_OP_ENA bit should be
enabled first.
0
SPKOUTP enable
0 = Disabled
1 = Enabled
Note that SPKOUTP is also
controlled by
SPKP_SPKVDD_ENA. When
powering up SPKOUTP, the
SPKP_OP_ENA bit should be
enabled first
0
Speaker output mixer enable
0 = Disabled
1 = Enabled
To enable the output PGA and mixers, the reference voltage VMID and the bias current must also be
enabled. See “Reference Voltages and Master Bias” for details of the associated controls VMID_SEL
and BIAS_ENA.
Note that the Line output, Speaker outputs, Speaker PGA mixer and Speaker PGA are all muted by
default. The required signal paths must be un-muted using the control bits described in the respective
tables below.
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