CS4341A Datasheet, PDF (9/32 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
LRCK
SCLK
S D IN
Left Channel
R ig ht C h a n n el
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 3. Left Justified up to 24-Bit Data
LRCK
SCLK
Left Channel
R ig h t C h a n n e l
SD IN MSB
LSB +1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1 MSB
LSB +1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1 MSB
3 2 clo cks
Figure 4. Right Justified Data
3.5 De-Emphasis Control
The device includes on-chip digital de-emphasis. The Mode Control 2 bits select either the 32, 44.1, or 48
kHz de-emphasis filter. Figure 5 shows the de-emphasis curve for F_s equal to 44.1 kHz. The frequency
response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see
section 5.2.3 for the desired de-emphasis control.
NOTE: De-emphasis is only available in Single-Speed Mode.
G ain
dB
T1=50 µs
0dB
-1 0d B
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 5. De-Emphasis Curve
3.6 Recommended Power-up Sequence
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to
the appropriate frequences, as discussed in section 3.2. In this state, the control port is reset to its
default settings and VQ will remain low.
2. Bring RST high. The device will remain in a low power state with VQ low.
3. Load the desired register settings while keeping the PDN bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximatel y 50µS
when the POR bit is set to 0. If the POR bit is set to 1, see section 3.7 for a complete description
of power-up timing.
DS582PP1
9