CS4341A Datasheet, PDF (26/32 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
Parameters
LRCK Duty Cycle
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Frequency
Symbol
Single-Speed Mode Fs
Double-Speed Mode Fs
Quad-Speed Mode Fs
MCLKDIV Disabled
t_sclkl
t_sclkh
Min
1.024
45
4
50
100
40
20
20
-
MCLKDIV Enabled
-
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
t_slrd
20
t_slrs
20
t_sdlrs
20
t_sdh
20
Max
51.2
55
50
100
200
60
-
-
M------C----L----K---
2
M------C----L----K---
4
-
-
-
-
Units
MHz
%
kHz
kHz
kHz
%
ns
ns
Hz
Hz
ns
ns
ns
ns
LRCK
SCLK
SDIN
t _slrd
t _slrs
t _sclkh
t _sclkl
t _sdlrs
t _sdh
Figure 19. Serial Input Timing
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DS582PP1