CS4341A Datasheet, PDF (12/32 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
3.9.2b I²C Read
To read from the device, follow the procedure below while adhering to the control port
Switching Specifications.
1) Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits
must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must
be 1. The eighth bit of the address byte is the R/W bit.
2) After transmitting an acknowledge (ACK), the device will then transmit the contents of
the register pointed to by the MAP. The MAP register will contain the address of the last
register written to the MAP, or the default address (see section 8.3) if an I²C read is the first
operation performed on the device.
3) Once the device has transmitted the contents of the register pointed to by the MAP, issue
an ACK.
4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive
registers. Continue providing a clock and issue an ACK after each byte until all the desired
registers are read, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is nec-
essary to initiate a repeated START condition and follow the procedure detailed from step
1. If no further reads from other registers are desired, initiate a STOP condition to the bus.
SDA
0 01 000
AD0
NOTE
R/W ACK
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Sta rt
Stop
N O TE: If operation is a w rite, this byte contains the Me mory Address Pointer, MAP. If
operation is a read, this byte contains the data of the register pointed to by th e MAP.
Figure 6. Control Port Timing, I²C Mode
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DS582PP1