CS4341A Datasheet, PDF (28/32 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)
Parameter
SPI Mode
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol
(Note 6)
(Note 7)
(Note 8)
(Note 8)
f_sclk
t_srs
t_spi
t_csh
t_css
t_scl
t_sch
t_dsu
t_dh
t_r2
t_f2
Min
-
500
500
1.0
20
66
66
40
15
-
-
Max
Unit
6
MHz
-
ns
-
ns
-
µs
-
ns
-
ns
-
ns
-
ns
-
ns
100
ns
100
ns
Notes: 6. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
7. Data must be held for sufficient time to bridge the transition time of CCLK.
8. For f_sclk < 1 MHz.
RST
t _srs
CS
CCLK
C D IN
t _spi t _css
t _scl t _sch
t _csh
t _r2
t _f2
t _dsu t _dh
Figure 21. Control Port Timing - SPI Mode
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DS582PP1