CS4341A Datasheet, PDF (27/32 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Inputs: Logic
0 = AGND, Logic 1 = VA)
Parameter
Symbol
Min
I²C Mode
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 5)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_rc, t_rc
-
Fall Time SCL and SDA
t_fc, t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Max
100
-
-
-
-
-
-
-
-
1
300
-
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
Notes: 5. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
RST
t _irs
S to p
S ta rt
SDA
t _buf
t _hdst
t _high
R e pe ate d
S ta rt _{t rd}
t _hdst
S to p
t _fd
t _fc
t _susp
SCL
t
lo w
t
hdd
t _sud t _ack
t _sust
t _rc
Figure 20. Control Port Timing - I²C Mode
DS582PP1
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