CS4341A_04 Datasheet, PDF (8/34 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
3.3 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK)
clocks. The LRCK, defined also as the input sample rate (F_s), must be synchronously derived from the
MCLK according to specified ratios. The specified ratios of MCLK to LRCK for each Speed Mode, along
with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5.
Sample Rate
(kHz)
32
44.1
48
Sample Rate
(kHz)
64
88.2
96
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
MCLK (MHz)
512x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
Table 3. Single-Speed Mode Standard Frequencies
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
MCLK (MHz)
256x
16.3840
22.5792
24.5760
384x
24.5760
33.8688
36.8640
Table 4. Double-Speed Mode Standard Frequencies
1024x*
32.7680
45.1584
49.1520
512x*
32.7680
45.1584
49.1520
Sample Rate
(kHz)
176.4
192
128x
22.5792
24.5760
MCLK (MHz)
192x
33.8688
36.8640
Table 5. Quad-Speed Mode Standard Frequencies
256x*
45.1584
49.1520
* Requires MCLKDIV bit = 1 in the Mode Control 1 register (address 00h).
3.4 Digital Interface Format
The device will accept audio samples in several digital interface formats. The desired format is selected
via the DIF0, DIF1 and DIF2 bits in the Mode Control 2 register (see section 5.2.2) . For an illustration of
the required relationship between LRCK, SCLK and SDIN, see Figures 2-4.
LRCK
SCLK
SDIN
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
Figure 2. I²S Data
+5 +4 +3 +2 +1 LSB
8
DS582F2