CS4341A_04 Datasheet, PDF (2/34 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................... 5
2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 6
3. APPLICATIONS ........................................................................................................................ 7
3.1 Upgrading from the CS4341 to the CS4341A .................................................................... 7
3.2 Sample Rate Range/Operational Mode Detect .................................................................. 7
3.2.1 Auto-Detect Enabled ............................................................................................. 7
3.2.2 Auto-Detect Disabled ............................................................................................ 7
3.3 System Clocking ................................................................................................................ 8
3.4 Digital Interface Format ...................................................................................................... 8
3.5 De-Emphasis Control ......................................................................................................... 9
3.6 Recommended Power-up Sequence ................................................................................. 9
3.7 Popguard^® Transient Control ........................................................................................... 10
3.7.1 Power-up ............................................................................................................. 10
3.7.2 Power-down ........................................................................................................ 10
3.7.3 Discharge Time ................................................................................................... 10
3.8 Grounding and Power Supply Arrangements .................................................................. 10
3.9 Control Port Interface ....................................................................................................... 11
3.9.1 Rise Time for Control Port Clock ......................................................................... 11
3.9.2 MAP Auto Increment ........................................................................................... 11
3.9.3 I²C Mode ............................................................................................................. 12
3.9.3a I²C Write ............................................................................................... 12
3.9.3b I²C Read .............................................................................................. 13
3.9.4 SPI Mode ............................................................................................................ 14
3.9.4a SPI Write .............................................................................................. 14
3.10 Memory Address Pointer (MAP) .............................................................................. 15
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is
provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders,
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