CS4341A_04 Datasheet, PDF (11/34 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
3.9 Control Port Interface
The control port is used to load all the internal register settings (see section 5). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interference
problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I²C or SPI.
Notes: MCLK must be applied during all I²C communication.
3.9.1 Rise Time for Control Port Clock
When excess capacitive loading is present on the I²C clock line, pin 6 (SCL/CCLK) may not have
sufficient hysteresis to meet the standard I²C rise time specification. This prevents the use of com-
mon I²C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt
Trigger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341A. This will not
affect the operation of the I²C bus as pin 6 is an input only.
VA
SCL
Pin 6
Figure 6. I²C Buffer Example
3.9.2 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit
(also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes
or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written,
allowing block reads or writes of successive registers.
DS582F2
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