CS4341A_04 Datasheet, PDF (31/34 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)
SPI Mode
Parameter
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol
Min
f_sclk
-
t_srs
500
(Note 9)
t_spi
500
t_csh
1.0
t_css
20
t_scl
66
t_sch
66
t_dsu
40
(Note 10)
t_dh
15
(Note 11)
t_r2
-
(Note 11)
t_f2
-
Max
Unit
6
MHz
-
ns
-
ns
-
µs
-
ns
-
ns
-
ns
-
ns
-
ns
100
ns
100
ns
Notes: 9. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For f_sclk < 1 MHz.
RST
t _srs
CS
CCLK
C D IN
t _spi t _css
t _scl t _sch
t _csh
t _r2
t _f2
t _{dsu t dh}
Figure 20. Control Port Timing - SPI Mode
DS582F2
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