CS4341A_04 Datasheet, PDF (30/34 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC with Volume Control

CS4341A
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
(Inputs: Logic 0 = AGND, Logic 1 = VA)
I²C Mode
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 7)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL
(Note 8)
t_rc
-
Fall Time SCL
t_fc
-
Rise Time of SDA
t_rd
-
Fall Time SDA
t_fd
-
Setup Time for Stop Condition
t_susp
4.7
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
25
ns
25
ns
1
µs
300
ns
-
µs
Notes: 7. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
8. See “Rise Time for Control Port Clock” on page 11. for a recommended circuit to meet rise time
specification.
RST
t _irs
Stop
S ta rt
R epeated
S ta rt
SDA
t _buf
t _hdst
t _high
t _hdst
tf
SCL
t _low
t _hdd
t _sud
t _sust
tr
Figure 19. Control Port Timing - I²C Mode
Stop
t _susp
30
DS582F2