CS4281 Datasheet, PDF (8/36 Pages) Cirrus Logic – CrystalClear PCI Audio interface

CS4281
CrystalClear™ PCI Audio Interface
EEPROM TIMING CHARACTERISTICS Note 4. (T_A = 0 to 70 °C, PCIVDD = CVDD = VAUX =
CRYVDD = 3.3 V; VDD5REF = 5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V,
Logic 1 = 3.3 V; Timing reference levels = 1.4 V; PCI clock frequency = 33 MHz; unless otherwise noted)
Parameter
Symbol
Min
EECLK Low to EEDAT Data Out Valid
t_AA
0
Start Condition Hold Time
t_HD:STA
5.0
EECLK Low
t_LEECLK
10
EECLK High
t_HEECLK
10
Start Condition Setup Time (for a Repeated Start Condition)
t_SU:STA
5.0
EEDAT In Hold Time
t_HD:DAT
0
EEDAT In Setup Time
t_SU:DAT
250
EEDAT/EECLK Rise Time
(Note 18)
t_R
-
EEDAT/EECLK Fall Time
t_F
-
Stop Condition Setup Time
t_SU:STO
5.0
EEDAT Out Hold Time
t_DH
0
Max
Units
7.0
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
-
µs
Notes: 18. Rise time on EEDAT is determined by the capacitance on the EEDAT line with all connected gates and
the required external pull-up resistor.
EECLK
EEDAT (IN)
t _SU:STA
EEDAT (OUT)
EEDAT (OUT)
t_F
t _HEECLK
t _LEECLK
t _HD:DAT
t _HD:STA
t _AA
t _DH
t _SU:DAT
Figure 4. EEPROM Timing
t_R
t _SU:STO
CIRRUS LOGIC PRODUCT DATA SHEET
8
DS308PP4