CS4281 Datasheet, PDF (6/36 Pages) Cirrus Logic – CrystalClear PCI Audio interface

CS4281
CrystalClear™ PCI Audio Interface
PCI INTERFACE PINS (T_A = 0 to 70° C; PCIVDD = CVDD = VAUX = CRYVDD = 3.3 V; VDD5REF =
5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V)
Parameter
PCICLK cycle time
PCICLK high time
PCICLK low time
PCICLK to signal valid delay - bused signals
PCICLK to signal valid delay - point to point
Float to active delay
(Note 15)
Active to Float delay
(Note 15)
Input Set up Time to PCICLK - bused signals
Input Set up Time to PCICLK - point to point
Input hold time for PCICLK
Reset active to output float delay
(Notes 15, 16, 17)
Symbol
t_cyc
t_high
t_low
t_val
t_val(p+p)
t_on
t_off
t_su
t_su(p+p)
t_h
t_rst-off
Min
30
11
11
2
2
2
-
7
10, 12
0
-
Max
Unit
-
ns
-
ns
-
ns
11
ns
12
ns
-
ns
28
ns
-
ns
-
ns
-
ns
30
ns
Notes: 15. For Active/Float measurements, the Hi-Z or “off” state is when the total current delivered is less than or
equal to the leakage current. Specification is guaranteed by design, not production tested.
16. RST# is asserted and de-asserted asynchronously with respect to PCICLK.
17. All PCI output drivers are asynchronously floated when RST# is active. Note ASDOUT and ASYNC are
not affected by RST#.
PCICLK
RST#
t _off
t _on
OUTPUTS
Hi-Z
t _val
OUTPUTS
Valid
t _rst-off
t _su
INPUTS
t_h
Valid
Input
Figure 2. PCI Timing Measurement Conditions
CIRRUS LOGIC PRODUCT DATA SHEET
6
DS308PP4