CS4281 Datasheet, PDF (23/36 Pages) Cirrus Logic – CrystalClear PCI Audio interface

CS4281
CrystalClear™ PCI Audio Interface
EEPROM INTERFACE
The EEPROM configuration interface allows the connection of an optional external EEPROM device to
provide power-up configuration information. The external EEPROM is not required for proper operation;
however, in some applications power-up configuration settings other than the default values may be re-
quired to support specific Operating System compatibility requirements.
After a hardware reset, an internal state machine in the CS4281 will automatically detect the presence of
an external EEPROM device. If the EEPROM header is correct, then EEPROM data is loaded into the Sub-
system ID and Subsystem Vendor ID fields at FCh in Configuration Space, along with four bytes of gen-
eral configuration information loaded into the CFLR register in Configuration Space. If the header data is
invalid, the data transfer is aborted. After power-up, the host can read or write from/to the EEPROM device
by accessing specific registers in the CS4281. Cirrus Logic provides software to read and write the EE-
PROM.
The two-wire interface for the optional external EEPROM
CS4281
3.3 V 3.3 V
device is depicted in Figure 13. During data transfers, the
data line (EEDAT) can change state only while the clock
4.7 kΩ
signal (EECLK) is low. A state change of the data line
EEDAT
EECLK
2-wire
Serial
EEPROM
while the clock signal is high indicates a start or stop con-
dition to the EEPROM device.
The EEPROM device read access sequence is shown in the
Figure 13. External EEPROM Connection ^{Figure 14. The timing follows that of a random read se-}
quence. The CS4281 first performs a “dummy” write oper-
ation, then generates a start condition followed by the slave
device address and the byte address of zero. The CS4281 always begins access at byte address zero and
continues access a byte at a time, using a sequential read, until all needed bytes in the EEPROM are read.
Since only 9 bytes are needed, the smallest EEPROM available will suffice.
CS4280
Part
Bank
Start _Address ^Write _Address
Start
Part
Address
Read
S1 0 1 0 0 0 0 0A0 0 0 0 0 0 0 0AS1 0 1 0 0 0 0 1A
No
Acknowledge Acknowledge
Stop
Data A
Data 1 P
EEPROM
Acknowledge
Data
Figure 14. EEPROM Read Sequence
GENERAL PURPOSE I/O PINS
Some CS4281 pins are internally multiplexed to serve different functions depending on the CS4281 driver.
The CS4281 general purpose functionality includes PME# assertion and interrupt functionality. Please
contact Cirrus Logic’s PC Audio support group for more information on the flexibility of the CS4281
GPIO pins.
CIRRUS LOGIC PRODUCT DATA SHEET
DS308PP4
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