CS4281 Datasheet, PDF (17/36 Pages) Cirrus Logic – CrystalClear PCI Audio interface

CS4281
CrystalClear™ PCI Audio Interface
GP1PT
GP1ST
GP1W
GP3OE
GP3PT
GP3ST
GP3W
GPIO1 input Polarity/output Type. When ASDIN2/GPIO1 is not configured as ASDIN2:
When ASDIN2/GPIO1 pin is configured as an input (GP1OE = 0), this bit sets the polarity.
0 - active low input
1 - active high input
When ASDIN2/GPIO1 pin is configured as an output (GP1OE = 1), this bit sets the type
0 - CMOS output
1 - open drain output
GPIO1 input Sticky. Assumes GP1OE = 0 and pin not configured for ASDIN2.
1 - GPIO1 input pin is latched, for edge sensitive inputs, and presented on the GP1S bit. The
GP1S bit is cleared by writing a 0 to GP1S.
0 - GPIO1 input pin (after GP1PT) is presented on GP1S bit for level sensitive inputs.
GPIO1 Wake. When set, GPIO1 can cause a wake-up event (asserts PME#). GP1ST must be
set sticky for this bit to be effective and the pin must not be configured for ASDIN2.
Output Enable GPIO3: Setting this bit enables the output buffer allowing writes to the GP3D bit
to be presented on the GPIO3 pin. Note that in backwards-compatible sockets, this pin is a
PCI power supply pin.
0 - Output disabled, pin is configured as an input (reset default)
1 - Output enabled
GPIO3 input Polarity/output Type.
When the GPIO3 pin is configured as an input (GP3OE = 0), this bit sets the polarity.
0 - active low input
1 - active high input
When the GPIO3 pin is configured as an output (GP3OE = 1), this bit sets the type
0 - CMOS output
1 - open drain output
GPIO3 input Sticky. Assumes GP3OE = 0.
1 - GPIO3 input pin is latched, for edge sensitive inputs, and presented on the GP3S bit. The
GP3S bit is cleared by writing a 0 to GP3S.
0 - GPIO3 input pin (after GP3PT) is presented on GP3S bit for level sensitive inputs.
GPIO3 Wake. When set, GPIO3 can cause a wake-up event (asserts PME#). GP3ST must be
set sticky for this bit to be effective.
Serial Port Power Management Control (SPMC)
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GIPPEN GISPEN
EESPD ASDI2E res
WUP2 WUP1 ASYN RSTN
Address: PCI CFG: ECh, Read-Write if CWPR configured, otherwise Read-Only
Definition: Supports power management of the AC Link and the enable for ASDIN2. This register is unaffected
by the PCI RST# signal.
Bit Descriptions:
RSTN
Reset NOT!: This bit controls the ARST# pin. Note the negative sense of the bit, which
matches the active low output pin definition. The ARST# pin is a logical OR of RSTN with the
PCI reset pin RST#.
0 = ARST# active, AC-Link and Codec reset (reset default)
1 = ARST# inactive, AC-Link and Codec not reset (normal operation).
ASYN
Asynchronous ASYNC Assertion: This bit allows the unclocked assertion of the ASYNC pin for
AC-Link management protocol requirements.
0 = Normal ASYNC generation (reset default)
1 = Force ASYNC high
CIRRUS LOGIC PRODUCT DATA SHEET
DS308PP4
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