CS4281 Datasheet, PDF (18/36 Pages) Cirrus Logic – CrystalClear PCI Audio interface

CS4281
CrystalClear™ PCI Audio Interface
WUP1
WUP2
GIPPEN
GISPEN
EESPD
ASDI2E
Wakeup for primary input: This bit indicates that a Codec attached to the ASDIN pin signaled a
wake-up event by forcing a low-to-high transition on ASDIN while the AC-Link is down. This bit
remains set until host driver software issues a warm reset of the AC-Link by setting the ASYN
bit; specifically, the falling edge of the ASYNC warm reset pulse clears this bit.
0 = No wake-up event signaled by ASDIN
1 = Wake-up event signaled by ASDIN
Wakeup for secondary input: This bit indicates that a Codec attached to the ASDIN2 pin
signaled a wake-up event by forcing a low-to-high transition on ASDIN2 while the AC-Link is
down. This bit remains set until host driver software issues a warm reset of the AC-Link by
setting the ASYN bit; specifically, the falling edge of the ASYNC warm reset pulse clears this
bit.
0 = No wake-up event signaled ASDIN2
1 = Wake-up event signaled by ASDIN2
GP_INT Primary PME# Enable for primary ASDIN2 Slot 12 data. When set, allows Primary
Codec’s slot 12 to generate a PME event when GP_INT goes from 0 to a 1.
GP_INT Secondary PME# Enable for secondary ASDIN2 Slot 12 data. When set, allows the
Secondary Codec to generate a PME event when GP_INT goes from 0 to a 1.
EEPROM Serial Port Disable. When set, the EEPROM engine is disabled and does NOT try
and read the EERPOM on a power-on reset. The two EEPROM pins are also disconnected
from the EEPROM engine. When clear, the EEPROM engine is enabled and goes out on the
EEPROM port and tries to read the EEPROM after a power-on reset.
ASDIN2 Enable.
0 = ASDIN2 function disabled (reset default) (converts to extended GPIO1).
1 = ASDIN2 function enabled (implies a Secondary Codec is attached)
Configuration Load Register (CFLR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CB37 CB36 CB35 CB34 CB33 CB32 CB31 CB30 CB27 CB26 CB25 CB24 CB23 CB22 CB21 CB20
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CB17 CB16 CB15 CB14 CB13 CB12 CB11 CB10 CB07 CB06 CB05 CB04 CB03 CB02 CB01 CB00
Address: PCI CFG: F0h, Read-Write if CWPR configured, otherwise Read-Only
Definition:
The Configuration Load Register provides a host port for reading of four bytes of device configura-
tion options from EEPROM. The BIOS can pre-load this register by writing to it in configuration
space. The following bit descriptions are for driver information only as these bits have no direct
hardware affect. When using the Cirrus software drivers, contact Cirrus before using any of these
bits as they may have pre-defined meanings.
Bit Descriptions:
CB0[7:0] This bit field returns the first configuration byte.
CB1[7:0] This bit field returns the second configuration byte.
CB2[7:0] This bit field returns the third configuration byte
CB3[7:0] This bit field returns the fourth configuration byte.
CIRRUS LOGIC PRODUCT DATA SHEET
18
DS308PP4