CS4235 Datasheet, PDF (72/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
run condition) will be read by the DMA inter-
face. A sample will not be overwritten while the
DMA interface is in the process of transferring
the sample.
Should an underrun condition occur in a play-
back case the last valid sample will be output
(assuming DACZ = 0) to the digital mixer. This
will mask short duration error conditions. When
the next complete sample arrives from the host
computer the data stream will resume on the
next sample clock.
The overrun and underrun error bits in the Alter-
nate Feature Status register, I24, are cleared by
first clearing the condition that caused the over-
run or underrun error, followed by writing the
particular bit to a zero. As an example, to clear
the playback underrun bit PU, first a sample
must be sent to the WSS Codec, and then the PU
bit must be written to a zero.
DIGITAL HARDWARE DESCRIPTION
The best example of hardware connection for the
different sections of this part is the Reference
Design Data Sheet. The Reference Design Data
Sheet contains all the schematics, layout plots
and a Bill of Materials; thereby providing a com-
plete example.
Bus Interface
The ISA bus interface is capable of driving a
24mA data bus load and therefore does not re-
quire any external data bus buffering. See the
Reference Design Data Sheet for a typical con-
nection diagram.
Volume Control Interface
Three hardware master volume control pins are
supported: volume up, volume down, and mute.
Hardware volume control is enabled by setting
the VCEN bit in the Hardware Configuration
data, byte 7 (Misc. Config. Byte). Once VCEN
is set, the XTAL1/ACDCS/DOWN pin converts
to the volume down function. The volume con-
72
trol pins affect the master volume control output
after the analog output mixer. The UP and
DOWN pins, when low, increment and decre-
ment the master volume. These two pins would
use SPST momentary switches. The MUTE pin
can either be momentary or non-existent where
pressing up and down simultaneously mutes the
output volume. The circuit in Figure 16, contains
optional resistors for EMI and ESD protection;
however, the capacitors are required for switch
debounce.
UP
DOWN
MUTE
100 ^Ω
10 nF
100 Ω
10 nF
100 Ω
10 nF
Up
Down
Mute
GND
Figure 16. Volume Control Circuit
Pressing the up button, increments the volume.
Pressing the down button, decrements the vol-
ume. Holding either of these buttons in the low
state causes the volume to to continue changing.
The formats are selected by the VCF1 bit, Hard-
ware Configuration data, Global Config. byte.
When VCF1 = 0, the mute function is a momen-
tary switch (similar to up and down). When
MUTE goes low the master out volume mutes if
it was un-muted and vise-versa (the mute button
alternates between mute and un-mute). If the
master volume is muted and up or down is
pressed, the volume automatically un-mutes.
When VCF1 = 1, the MUTE pin is not used.
This is a two-button format where pressing up
and down simultaneously mutes the master vol-
ume. If the master volume is muted and up or
down is individually pressed, the volume auto-
matically un-mutes.
DS252PP2