CS4235 Datasheet, PDF (24/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
HW Config. Byte 17: CDbase Address Length,
Default = 00000100
D7 D6 D5 D4 D3 D2 D1 D0
CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
CAL7-CAL0
CDbase Address Length. Determines
the address length decode for the
primary CDROM address, CDbase.
CDbase must be on the same para-
graph boundry as the address lengh
decode.
00000001 - CDCS low for 1 byte
00000010 - CDCS low for 2 bytes
00000100 - CDCS low for 4 bytes
00001000 - CDCS low for 8 bytes
00010000 - CDCS low for 16 bytes
00100000 - CDCS low for 32 bytes
01000000 - CDCS low for 64 bytes
10000000 - CDCS low for 128 bytes
xxx - all others, RESERVED
Bytes 19 through 21 map the interrupt number to
the actual interrupt pins A - F. As shown in Ta-
ble 2, the byte 20 default is 0xB9; therefore,
IRQ C, which is the lower nibble, maps to the
ISA interrupt 9. Likewise IRQ D, which is the
upper nibble, maps to the ISA interrupt 11
(0Bh).
Byte 22 maps the DMA channel number to the
actual DMA pins A and B. As shown in the ta-
ble, the byte 22 default is 0x10; therefore,
DRQA/DACKA is the lower nibble which maps
to the ISA DMA channel 0. Likewise
DRQB/DACKB is the upper nibble which maps
to the ISA DMA channel 1.
Byte 23 maps DMA C and IRQ G. The lower
nibble maps DMA C and defaults to DMA 3.
The upper nibble supports a seventh IRQ,
IRQ G. The default is disabled (0), providing
backwards compatibility with other Cirrus Audio
parts. If IRQ G is connected to an ISA interrupt
(typically 10), then this byte must be modified to
reflect the hardware connection.
Hostload Procedure
This procedure is provided for backwards com-
patibility with the CS4236. Since the E²PROM
allows all resource and firmware patch data to be
loaded at power-up, this procedure is typically
only used with motherboard devices that do not
include an E²PROM. To download PnP resource
data from the host to the part’s internal RAM,
use the following sequence:
1. Configure Control I/O base address,
CTRLbase, by one of two methods: regular
PnP cycle or Crystal Key method.
a. The host can use the regular PnP cycle to
program the CTRLbase, and then place the
chip in the wait_for_key_state
b. If the Crystal Key method is used:
First, send the 32-byte Crystal key to I/O
address port (AP).
Second, configure logical device 2 base
address, CTRLbase, by writing to AP
(15h, 02h, 47h, xxh, xxh, 33h, 01h, 79h).
Note: The two xxh represent the base_ad-
dress_high and base_address_low
respectively. The default is: 01h, 20h.
2. Write 57h (Jump to ROM) command to
CTRLbase+5.
3. Download the PnP Resource data.
a. Send download command by writing AAh
to CTRLbase+5.
b. Send starting download address (4000h)
by writing low byte (00h) first, and then
high byte (40h) to CTRLbase+5.
c. Send the Hardware Configuration and re-
source data in successive bytes to
CTRLbase+5. This includes the Hardware
Configuration and the PnP resource data.
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