CS4235 Datasheet, PDF (64/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
Standard Synthesizer I/O Map
Address
Name
SYNbase+0
FM Status
SYNbase+0 FM Address 0
SYNbase+1
FM Data 0
SYNbase+2 FM Address 1
SYNbase+3
FM Data 1
Type
Read Only
Write Only
Read/Write
Write Only
Read/Write
CDROM INTERFACE
An IDE CDROM controller interface is provided
that supports Enhanced as well as Legacy IDE
CDROM drives. This interface includes two pro-
grammable chip selects and on-chip hardware to
map DMA and interrupt signals to the ISA bus.
Use of the CDROM interface requires an exter-
nal 1k E²PROM to support CDROM
Plug-and-Play, Hardware Configuration, and
firmware patch data.
There are five pins that make up the CDROM
interface which consist of:
CDCS - chip select, COMbase address
CDINT - interrupt, COMint
CDRQ - DMA request, COMdma
CDACK - DMA acknowledge, COMdma
ACDCS - alternate chip select, ACDbase
The four basic CDROM interface pins are multi-
function pins that default to the upper address
bits SA12 - SA15. To use the pins as a CDROM
interface, a 10 kΩ pulldown resistor must be
placed on MCLK.
The fifth CDROM pin ACDCS is multiplexed
with XCTL1/SINT/DOWN. This chip select sup-
ports the alternate CDROM chip select used for
status. The volume control pin DOWN has the
highest precedence; therefore, the VCEN bit
must be zero to use this pin for the CDROM in-
terface. Given that VCEN is zero, a 10 kΩ
pulldown resistor on SDOUT converts this pin to
ACDCS. The range of addresses that ACDCS
will respond to is programmable via the Hard-
ware Configuration data, byte 5, from one to
eight bytes (default = 1 byte).
To make the CDROM interface more flexible,
one global bit, located in the Hardware Configu-
ration data section - byte 7, allow control over
the polarity of the CDROM interrupt pin
CDINT. IHC defaults to 1 indicating that CDINT
is an active high interrupt. IHC is also control-
lable through CTRLbase+1.
CS4610 DSP SERIAL DATA PORT
The WSS Codec includes a CS4610 DSP serial
audio interface for transferring digital audio data
between the part and the CS4610 DC ’97 Audio
Accelerator serial device. When SPE is set
(MCE must be 1 to change SPE), the serial port
pins are enabled; otherwise, they are high-im-
pedance pins.
The DSP audio serial port is software enabled
via the SPE bit in the WSS Codec indirect regis-
ter I16 or from the Hardware Configuration data
in the EEPROM. The ISA interface is fully ac-
tive in this mode. The serial port data format is
always two’s complement 16-bit linear.
FSYNC and SCLK are always output from the
part when the serial port is enabled. The serial
port can be configured in one of four serial port
formats, shown in Figures 6-9. SF1 and SF0 in
I16 select the particular format. MCE in R0 must
be set to change SF1/0. Both left and right audio
words are always 16 bit two’s complement.
When the mono audio format is selected, the
right channel output is set to zero and the left
channel input is sent to both DAC channels.
The first format - SPF0, shown in Figure 6, is
called 64-bit enhanced. This format has 64
SCLKs per frame with a one bit period wide
FSYNC that precedes the frame. The first 16 bits
occupy the left word and the second 16 bits oc-
64
DS252PP2