CS4235 Datasheet, PDF (71/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
The act of writing a value to the Upper Base
register causes both Base registers to load the
Current Count register. DMA transfers are en-
abled by setting the PEN/CEN bit while
PPIO/CPIO is clear. (PPIO/CPIO can only be
changed while the MCE bit is set.) Once trans-
fers are enabled, each sample that is transferred
by a DMA cycle will decrement the Current
Count register until zero is reached. The next
sample after zero generates an interrupt and re-
loads the Current Count registers with the values
in the Base registers.
For all data formats the DMA Base registers
must be loaded with the number of samples, mi-
nus one, to be transferred between "DMA
Interrupts". A sample is one to four bytes wide
and is defined as all data taken at one instant in
time. Stereo and mono data contain the same
number of samples, and 8-bit data and 16-bit
data contain the same number of samples.
Symbolically:
DMA Base register₁₆ = N_S - 1
Where N_S is the number of samples transferred
between interrupts and the "DMA Base regis-
ter₁₆" consists of the concatenation of the upper
and lower DMA Base registers.
PLAYBACK DMA REGISTERS
The playback DMA registers (I14/15) are used
for sending playback data to the DACs in
MODE 2 and 3. In MODE 1, these registers
(I14/15) are used for both playback and capture;
therefore, full-duplex DMA operation is not pos-
sible.
When the playback Current Count register rolls
under, the Playback Interrupt bit, PI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Playback
Interrupt bit, PI (I24).
DS252PP2
CAPTURE DMA REGISTERS
The Capture DMA Base registers (I30/31) pro-
vide a second pair of Base registers that allow
full-duplex DMA operation. With full-duplex op-
eration capture and playback can occur
simultaneously. These registers are provided in
MODE 2 and 3 only.
When the capture Current Count register rolls
under, the Capture Interrupt bit, CI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Capture In-
terrupt bit, CI (I24).
WSS Codec Interrupt
The INT bit of the Status register (R2) always
reflects the status of the WSS Codec’s internal
interrupt state. A roll-over from any Current
Count register (DMA playback, DMA capture, or
Timer) sets the INT bit. This bit remains set until
cleared by a write of ANY value to Status regis-
ter (R2), or by clearing the appropriate bit or bits
(PI, CI) in the Alternate Feature Status register
(I24).
The Interrupt Enable (IEN) bit in the Pin Control
register (I10) determines whether the interrupt
assigned to the WSS Codec responds to the in-
terrupt event. When the IEN bit is low, the
interrupt is masked and the IRQ pin assigned to
the WSS Codec is held low. However, the INT
bit in the Status register (R2) always responds to
the counter.
Error Conditions
Data overrun or underrun could occur if data is
not supplied to or read from the WSS Codec in
an appropriate amount of time. The amount of
time for such data transfers depends on the fre-
quency selected within the WSS Codec.
Should an overrun condition occur during data
capture, the last whole sample (before the over-
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