CS42406 Datasheet, PDF (49/50 Pages) Cirrus Logic – 24-BIT, 192kHz 2-IN 6-OUT AUDIO CODEC

CS42406
9. REVISION HISTORY
Revision
PP1
PP2
PP3
PP4
PP5
Date
August 2003
March 2004
August 2004
December 2004
December 2004
Changes
Initial Release
Added Revision History Table.
Changed “Gain Error” from ±5% to ±10% in the ADC Analog Characteristics.
Removed “Inter Channel” and “Intra Channel Phase Deviation” specification on
page 11 and page 16.
Removed ADC & DAC FILT+ “Output Impedance” and “Current Source Sink” spec-
ification on page 19.
Changed maximum V_OL from 13% to 15% on page 20.
Changed MCLK min/max duty cycle from 40/60% to 45/55% on page 23.
Added Figure 37 on page 34.
Added lead free part numbers.
Corrected typographical errors.
Removed automotive part CS42406-DQZ ordering availability and performance
specifications.
Added Note 3 to 4 on page 8 limiting VA, VD and VL operation.
Modified table “Switching Characteristics - ADC Serial Audio Port” on page 23 to
highlight 256x and 384x mode.
Added “ADC_LRCK Frequency”, “SCLK Duty Cycle (Slave Mode)” and setup &
hold timing specifications in “Switching Characteristics - ADC Serial Audio Port” on
page 23.
Removed ADC_SCLK high/low timing and the “ADC_SCLK falling to SDOUT valid”
specifications from “Switching Characteristics - ADC Serial Audio Port” on page 23.
Modified Figures 24 to 27 on page 25 to reflect timing specifications.
Corrected Typical Connection Diagram, Figure 33 on page 29.
Added ADC_SCLK/ADC_LRCK ratio parameters in Table 1 to 2 on page 30.
Changed recommended anti-aliasing capacitor value from 2700 pF to 2200 pF in
Figure 36 “CS42406 Recommended Analog Input Buffer” on page 34.
Table 10. Revision History
49