CS42406 Datasheet, PDF (27/50 Pages) Cirrus Logic – 24-BIT, 192kHz 2-IN 6-OUT AUDIO CODEC

CS42406
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE Inputs: Logic
0 = GND, Logic 1 = VLC
Parameter
Symbol
Min
I²C Mode
SCL Clock Frequency
f_scl
-
DAC_RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 19)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_rc, t_rc
-
Fall Time SCL and SDA
t_fc, t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
(Note 20)
t_ack
-
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
(Note 21)
ns
Notes: 19.
20.
21.
Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
2^----5^---6^---5--×^-----F^----s^{- for Single-Speed Mode,} 1^----2^---8^----5-×^-----F^----s^-
for Double-Speed Mode, _{---------5----------}
64 × Fs
for Quad-Speed Mode.
DAC_RST
t _irs
Stop
Start
SDA
t _buf
t _hdst
t _high
Repeated
Start
t _rd
Stop
t _fd
t _hdst
t _fc
t _susp
SCL
t
low
t
hdd
t _sud t _ack
t _sust
t _rc
Figure 31. Control Port Timing - I²C Mode
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