CS42406 Datasheet, PDF (31/50 Pages) Cirrus Logic – 24-BIT, 192kHz 2-IN 6-OUT AUDIO CODEC

CS42406
DAC_M1 DAC_M0 Input Sample Rate (Fs)
0
0 4 kHz - 50 kHz
0
1 32 kHz - 48 kHz
1
0 50 kHz - 100 kHz
1
1 100 kHz - 200 kHz
MODE
Single-Speed Mode (without De-emphasis)
Single-Speed Mode (with De-emphasis)
Double-Speed Mode
Quad-Speed Mode
Table 3. CS42406 Stand Alone DAC Operational Modes
4.1.2b Control Port Mode
The DAC’s operate in one of three operational modes determined by the FM bits (see section 6.1.4) in
Control Port mode. Sample rates outside the specified range for each mode are not supported.
FM1
0
0
1
1
FM0
0
1
0
1
Input Sample Rate (Fs)
4 kHz - 50 kHz
50 kHz - 100 kHz
100 kHz - 200 kHz
Reserved
MODE
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Reserved
Table 4. CS42406 Control Port DAC Operational Modes
4.2 ADC Serial Port Operation as Either a Clock Master or Slave
The CS42406 ADC serial port supports operation as either a clock master or slave. As a clock master, the
ADC_LRCK and ADC_SCLK pins are outputs with the left/right and serial clocks synchronously generated on-chip.
As a clock slave, the ADC_LRCK and ADC_SCLK pins are inputs and require the left/right and serial clocks to be
externally generated. The selection of clock master or slave is made via the ADC_Mx pins as shown in Table 5.
ADC_M1
0
0
1
1
ADC_M0
0
1
0
1
MODE
Clock Master, Single-Speed Mode
Clock Master, Double-Speed Mode
Clock Master, Quad-Speed Mode
Clock Slave, All Speed Modes
Table 5. CS42406 ADC Serial Port Mode Control
4.2.1 Operation as a Clock Master
As a clock master, ADC_LRCK and ADC_SCLK operate as outputs. The left/right and serial clocks are internally
derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in
Figure 34.
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