CS42406 Datasheet, PDF (23/50 Pages) Cirrus Logic – 24-BIT, 192kHz 2-IN 6-OUT AUDIO CODEC

CS42406
SWITCHING CHARACTERISTICS - ADC SERIAL AUDIO PORT Logic “0” = GND =
0 V; Logic “1” = VLS, C_L = 20 pF.
NOTE: Certain parameters depend on the 256x/384x (pin6) mode setting and are separated below.
Parameter
Symbol Min
Typ
Max Unit
MCLK Duty Cycle
45
-
55
%
Master Mode
ADC_SCLK falling to ADC_LRCK
ADC_SCLK falling to SDOUT valid
Slave Mode
t_mslr
-20
-
20
ns
t_sdo
0
-
32
ns
Single-Speed*
ADC_LRCK Frequency
MCLK = 256, 384 Fs (÷1 or 1.5) Fs
4
-
50
kHz
(Note 18)
MCLK = 512, 768 Fs (÷2 or 3) _Fs
43
50
kHz
ADC_LRCK Duty Cycle
40
-
60
%
SDOUT valid before ADC_SCLK rising
SDOUT valid after ADC_SCLK rising
ADC_SCLK falling to ADC_LRCK edge
Double-Speed*
t_stp
10
-
-
ns
t_hld
5
-
-
ns
t_slrd
-20
-
20
ns
ADC_LRCK Frequency
MCLK = 128, 192 Fs (÷1 or 1.5) Fs
50
-
100 kHz
(Note 18)
MCLK = 256, 384 Fs (÷2 or 3) Fs
86
100 kHz
ADC_LRCK Duty Cycle
40
-
60
%
SDOUT valid before ADC_SCLK rising
SDOUT valid after ADC_SCLK rising
ADC_SCLK falling to ADC_LRCK edge
Quad-Speed*
t_stp
10
-
-
ns
t_hld
5
-
-
ns
t_slrd
-20
-
20
ns
ADC_LRCK Frequency
(Note 18)
MCLK = 128 Fs (÷2 or 3) Fs
172
-
200 kHz
ADC_LRCK Duty Cycle
40
-
60
%
SDOUT valid before ADC_SCLK rising
SDOUT valid after ADC_SCLK rising
ADC_SCLK falling to ADC_LRCK edge
t_stp
10
-
t_hld
5
-
t_slrd
-8
-
-
ns
-
ns
8
ns
23