CS4270_06 Datasheet, PDF (48/49 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

Release
PP1
CS4270
Changes
– Update Release after B0 chip validation
– Changed value of A/D shunt capacitor from 2200 pF to 220 pF in Figure 18
– Added “single ended input” to “A/D Features” on page 1 and “single ended output” to “D/A
Features” on page 1
– Added “3.3 V or 5 V core supply” to “System Features” on page 1
– Added package/grade & ordering info to “General Description” on page 2
– Changed note 2. in Figure 1
– Moved ordering info to Section 12
– Moved Typical Connection Diagram to Section 3
– Removed SOIC data from Thermal Characteristics Table on page 9
– Changed DAC THD+N specs in “DAC Analog Characteristics - Commercial Grade” on
page 10 and “DAC Analog Characteristics - Automotive Grade” on page 10
– Changed DAC Full Scale Output Voltage specs in “DAC Analog Characteristics - all Modes”
on page 11
– Revised specifications in “DAC Combined Interpolation & on-Chip Analog FIlter Response”
on page 12
– Changed A/D THD+N and Full Scale Input Voltage specs in “ADC Analog Characteristics -
Commercial Grade” on page 13 and “ADC Analog Characteristics - Automotive Grade” on
page 14
– Specified A/D input circuit for performance specs in “ADC Analog Characteristics -
Commercial Grade” on page 13 and “ADC Analog Characteristics - Automotive Grade” on
page 14
– Revised specifications in “ADC Digital Filter CharacteristicS” on page 15
– Changed PSRR spec in “DC Electrical Characteristics” on page 16
– Revised Serial Audio Port specifications and acronyms in “Switching Characteristics - Serial
Audio Port” on page 17
– Replaced serial port timing diagrams with Figure 4, Figure 5, Figure 6, Figure 7 and
Figure 8, revised Note 17 and Note 18.
– Revised power up sequence text in “Recommended Power-Up Sequence - Access to
Control Port Mode” on page 24
– Changed text in “Input Connections” on page 28 to specify maximum source impedance for
A/D performance specifications in the A/D Specification Tables
– Added “A/D THD+N Performance vrs. Input Source Resistance” on page 28 and “A/D
Dynamic Range vrs. Input Source Resistance” on page 29
– Revised text in “Input Connections” on page 28 that describes A/D input attenuator (resistor
divider) circuit
– Replaced Figure 18 on page 30
– Moved Parameter Definitions to Section 10
– Moved “Filter Plots” to Section 9 and updated all plots
– Moved “Package Dimensions” to Section 11 and updated dimensions data
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DS686PP1