CS4270_06 Datasheet, PDF (31/49 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4270
AOUTx
LPF
CS4270
MUTEx
+V_EE
AC
Couple
560 Ω
-V_EE
+V_A
MMUN2111LT1
2 kΩ
10 kΩ
Audio
Out
47 kΩ
-V_EE
Figure 20. Suggested Active-Low Mute Circuit
5.6 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS4270’s in the sys-
tem. If only one MCLK source is needed, one solution is to place one CS4270 in Master Mode, and slave
all of the other CS4270’s to the one master. If multiple MCLK sources are needed, a possible solution
would be to supply all clocks from the same external source and time the CS4270 reset with the inactive
edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
5.7 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4270 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power
arrangements, with VA and VD connected to clean supplies. VD, which powers the digital filter, may be
run from the system digital supply (VD) or may be powered from the analog supply (VA) via a resistor. In
this case, no additional devices should be powered from VD. Power supply decoupling capacitors should
be as near to the CS4270 as possible, with the low value ceramic capacitor being the nearest. All signals,
especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted cou-
pling into the modulators. The VREF and VCOM decoupling capacitors, particularly the 0.1 µF, must be
positioned to minimize the electrical path from VREF and AGND. The CDB4270 evaluation board dem-
onstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the
CS4270 digital outputs only to CMOS inputs.
DS686PP1
31