CS4270_06 Datasheet, PDF (35/49 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

8. REGISTER DESCRIPTION
** All registers are read/write in I²C Mode and SPI Mode, unless otherwise noted**
CS4270
8.1 Chip ID - Address 01h
7
id<3>
6
id<2>
5
id<1>
4
id<0>
3
rev<3>
2
rev<2>
1
rev<1>
0
rev<0>
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID which is 1100b (01h) and the remaining
bits (b3:b0) are for the chip revision.
8.2 Power Control - Address 02h
7
Freeze
6
Reserved
5
PDN_ADC
4
Reserved
3
Reserved
2
Reserved
1
PDN_DAC
0
PDN
8.2.1 Freeze (Bit 7)
Function:
This function allows modifications to be made to certain Control Port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
below:
– Register 05h (Bits 7:0)
– Register 06h (Bits 7:0)
– Register 07h (Bits 7:0)
– Register 08h (Bits 7:0)
8.2.2 PDN_ADC (Bit 5)
Function:
The ADC portion of the device will enter a low-power state whenever this bit is set.
8.2.3 PDN_DAC (Bit 1)
Function:
The DAC portion of the device will enter a low-power state whenever this bit is set.
8.2.4 Power Down (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The contents of the control registers are
retained when the device is in power-down.
DS686PP1
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