CS4270_06 Datasheet, PDF (17/49 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = AGND = 0 V; Logic "1" = VD, C_L = 20 pF)
Parameter
Sample Rate
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
MCLK Specifications
MCLK Frequency
(Note 17)
tand-Alone Mode
Control Port Mode
MCLK Duty Cycle
Master Mode
LRCK Duty Cycle
SCLK Period (Note 18)
Symbol
Fs
Fs
Fs
fmclk
fmclk
t_sclkw
SCLK Duty Cycle
SCLK falling to LRCK edge
SCLK falling to SDOUT valid
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Slave Mode
LRCK Duty Cycle
SCLK Period
(Note 17)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
t_mslr
t_sdo
t_sdis
t_sdih
t_sclkw
t_sclkw
t_sclkw
SCLK Duty Cycle
SCLK falling to LRCK edge
t_slrd
SDOUT valid before SCLK rising
t_stp
SDOUT valid after SCLK rising
t_hld
SDIN valid to SCLK rising setup time
t_sdis
SCLK rising to SDIN hold time
t_sdih
Min
4
50
100
1.024
1.024
40
-
-
-
-20
-
16
20
40
---------1-----------
( 128 ) F s
(^---6^---4^--1-)^---F^----s^-
(^---6^---4^--1-)^---F^----s^-
45
-20
10
5
16
20
Typ
-
-
-
-
-
50
50
--------1---------
( 64 ) F s
50
-
-
-
-
50
-
-
-
50
-
-
-
-
-
CS4270
Max
Unit
54
kHz
108
kHz
216
kHz
55.296
55.296
60
MHz
MHz
ns
-
%
-
s
-
%
20
ns
32
ns
-
ns
-
ns
60
%
-
s
-
s
-
s
55
ns
20
ns
-
ns
-
ns
-
ns
-
ns
17. In Control Port Mode, MCLK Frequency and Functional Mode Select bits must be configured according
to Table 5, Table 8, and Table 12.
18. t_{sclkw =} t_{sclkh +} t_sclkl in Figures 5 and 7.
DS686PP1
17