CS4270_06 Datasheet, PDF (26/49 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo Audio CODEC

CS4270
Double-Speed
Quad-Speed
128
32, 48, 64
Fs
0
0
0
192
32, 48, 64
Fs
0
0
1
256
32, 48, 64
Fs
0
1
0
384
32, 48, 64
Fs
0
1
1
512
32, 64
Fs
1
0
0
64
32
Fs
0
0
0
96
48, 64
Fs
0
0
1
128
32, 64
Fs
0
1
0
192
48, 64
Fs
0
1
1
256
32, 64
Fs
1
0
0
Table 5. Clock Ratios - Control Port Mode (Continued)
5.2.5 Internal Digital Loopback
In Control Port Mode, the CS4270 supports an internal digital loopback mode in which the output of the
ADC is routed to the input of the DAC. This mode may be activated by setting the Digital Loopback bit in
the ADC & DAC Ctrl register (04h).
When this bit is set, the status of the DAC_DIF(4:3) bits in register 04h will be disregarded by the CS4270.
Any changes made to the DAC_DIF(4:3) bits while the Digital Loopback bit is set will have no impact on
operation until the Digital Loopback bit is released, at which time the Digital Interface Format of the DAC
will operate according to the format selected in the DAC_DIF(4:3) bits. While the Digital Loopback bit is
set, data will be present on the SDOUT pin in the format selected in the ADC_DIF(0) bit in register 04h.
5.2.6 Auto-Mute
The Auto-Mute function is controlled by the status of the Auto Mute bit in the Mute register. When set, the
DAC output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single
sample of non-static data will release the mute. Detection and muting are done independently for each
channel. The common mode on the output will be retained and the Mute Control pin for that channel will
become active during the mute period. The muting function is affected, similar to volume control changes,
by the Soft and ZeroCross bits in the Transition and Control register. The Auto Mute bit is set by default.
5.2.7 High-Pass Filter and DC Offset Calibration
The input circuitry driving the CS4270 may generate a small DC offset into the A/D converter. The CS4270
includes a high-pass filter after the decimator to remove any DC offset which could result in recording a
DC level, possibly yielding "clicks" when switching between devices in a multichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. The high-pass filter can be enabled if the hpf_freeze bit is set during normal operation, the current
value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be sub-
tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration
by:
1. Running the CS4270 with the high-pass filter enabled until the filter settles. See the Digital Filter
Characteristics for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS4270.
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