WM8310 Datasheet, PDF (46/291 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8310
Pre-Production
13 CLOCKING AND OSCILLATOR CONTROL
13.1 GENERAL DESCRIPTION
The WM8310 incorporates a 32.768kHz crystal oscillator in order to maintain the Real Time Clock
(RTC). An external crystal is normally required. Alternatively, a 32.768kHz signal may be input directly
on the XTI pin. The crystal oscillator and RTC are normally enabled at all times, including the OFF
and BACKUP power states. It is possible to disable the crystal oscillator in BACKUP for power-saving
RTC ‘unclocked’ mode if desired. The WM8310 clock functions are illustrated in Figure 16.
Figure 16 Clocking Configuration
The 32.768kHz crystal oscillator is enabled using the XTAL_ENA register. The crystal oscillator is
enabled in the OFF, ON and SLEEP states when XTAL_ENA is set. The status of the crystal
oscillator in BACKUP is selected using the XTAL_BKUPENA register.
Note that the XTAL_ENA field is set via OTP/ICE settings only; it cannot be changed by writing to the
control register. Also, if an external 32.768kHz signal is connected as an input to the XTI pin, and the
crystal is omitted, it is still required to set XTAL_ENA = 1 for normal operation.
The crystal oscillator can be disabled in the BACKUP state by setting the XTAL_BKUPENA register
bit to 0. This feature may be used to minimise the device power consumption in the BACKUP state,
as described in Section 20.5. The crystal oscillator is maintained in the BACKUP state if both
XTAL_ENA and XTAL_BKUPENA are set to 1.
A clock output signal CLKOUT is provided, for the purpose of clocking other devices. This output may
be driven by the 32.768kHz oscillator or by the output of a Frequency Locked Loop (FLL). The FLL
provides a flexible capability to generate a new clock signal either from the 32.768kHz oscillator or
from an external input CLKIN. The FLL is tolerant of jitter and may be used to generate a stable clock
signal from a less stable input reference. The FLL output can be routed to the CLKOUT pin.
The CLKOUT signal can be enabled or disabled directly by writing to the CLKOUT_ENA register in
the ON or SLEEP power states. The CLKOUT can also be controlled as part of the power state
transitions using the CLKOUT_SLOT and CLKOUT_SLP_SLOT register fields. See Section 11.3 for a
description of the state transition timeslots.
The CLKOUT pin may be configured as a CMOS output or as an Open-Drain output. At high
frequencies, the CMOS output is recommended. The CLKOUT signal is referenced to the DBVDD
power domain.
If the XTAL_INH bit is set, then an ‘ON’ state transition is delayed until the CLKOUT output is valid.
(Note that CLKOUT may be the crystal oscillator output, or may be the FLL output.) This may be
desirable if the CLKOUT signal is used as a clock for another circuit, to ensure that the CLKOUT
signal has been verified before the ‘ON’ state transition occurs. Note that the CLKOUT output is
always disabled in the OFF power state; it is typically enabled as part of the ‘ON’ state transition
sequence. Setting XTAL_INH = 1 ensures that the CLKOUT output cannot be enabled until the
source signal (crystal oscillator or FLL) has been verified.
The CLKOUT control fields are described in Table 16. Some of these controls may also be stored in
the integrated OTP memory. See Section 14 for details.
w
PP, May 2012, Rev 3.1
46