WM8310 Datasheet, PDF (148/291 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8310
ADDRESS
R16402
(4012h)
Interrupt Status
2
BIT
LABEL
7
CS2_EINT
6
CS1_EINT
R16410
(401Ah)
7
IM_CS2_EINT
Interrupt Status
2 Mask
6
IM_CS1_EINT
Table 93 Current Sink Interrupts
Pre-Production
DESCRIPTION
Current Sink 2 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Current Sink 1 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
23.2.11 REAL TIME CLOCK INTERRUPTS
The primary RTC_INT interrupt comprises two secondary interrupts as described in Section 20.3. The
secondary interrupt bits are defined in Table 94.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a RTC_INT interrupt. The secondary interrupt bits in R16401
(4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
R16401
(4011h)
Interrupt Status
1
BIT
LABEL
3
RTC_PER_EINT
2
RTC_ALM_EINT
R16409
(4019h)
3
IM_RTC_PER_EINT
Interrupt Status
1 Mask
2
IM_RTC_ALM_EINT
Table 94 Real Time Clock (RTC) Interrupts
DESCRIPTION
RTC Periodic interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
RTC Alarm interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
23.2.12 OTP MEMORY INTERRUPTS
The primary OTP_INT interrupt comprises two secondary interrupts as described in Section 14.5. The
secondary interrupt bits are defined in Table 95.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a OTP_INT interrupt. The secondary interrupt bits in R16402
(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
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PP, May 2012, Rev 3.1
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