WM8310 Datasheet, PDF (256/291 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8310
REGISTER BIT
ADDRESS
LABEL
DEFAULT
DESCRIPTION
110 = FVCO / 7
111 = FVCO / 8
Pre-Production
REFER TO
2:0 FLL_FRATIO
[2:0]
Recommended that this register is not changed from
default.
000 FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
Register 4093h FLL Control 2
000 recommended for high FREF
011 recommended for low FREF
REGISTER
ADDRESS
R16532
(4094h) FLL
Control 3
BIT
15:0
LABEL
DEFAULT
DESCRIPTION
FLL_K [15:0]
0000_0000 Fractional multiply for FREF
_0000_000 _{(MSB = 0.5)}
0
Register 4094h FLL Control 3
REFER TO
REGISTER
ADDRESS
R16533
(4095h) FLL
Control 4
BIT
14:5
3:0
LABEL
DEFAULT
DESCRIPTION
FLL_N [9:0] 01_0111_0 Integer multiply for FREF
111
(LSB = 1)
FLL_GAIN [3:0] 0000 Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1XXX = x 256
REFER TO
Register 4095h FLL Control 4
Recommended that this register is not changed from
default.
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PP, May 2012, Rev 3.1
256