WM8281 Datasheet, PDF (42/392 Pages) Cirrus Logic – Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation

WM8281
JTAG INTERFACE TIMING
t_CCY
TCK
(input)
TRST
t_CCH
t_CCL
(input)
t_RSU
t_RH
TMS
(input)
TDI
(input)
t_MSU
t_MH
TDO
(output)
t_DSU
t_DH
t_DD
Figure 12 JTAG Interface Timing
Test Conditions
The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.
CLOAD = 25pF (output pins). TCK slew (20% to 80%) = 5ns.
PARAMETER
JTAG Interface Timing
TCK cycle time
TCK pulse width high
TCK pulse width low
TMS setup time to TCK rising edge
TMS hold time from TCK rising edge
TDI setup time to TCK rising edge
TDI hold time from TCK rising edge
TDO propagation delay from TCK falling edge
TRST setup time to TCK rising edge
TRST hold time from TCK rising edge
TRST pulse width low
SYMBOL
TCCY
TCCH
TCCL
TMSU
TMH
TDSU
TDH
TDD
TRSU
TRH
MIN
50
20
20
1
2
1
2
0
3
3
20
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
17
ns
ns
ns
ns
42
Rev 4.0