WM8281 Datasheet, PDF (272/392 Pages) Cirrus Logic – Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation

272
WM8281
REGISTER BIT
ADDRESS
2:0
LABEL
OPCLK_SEL
[2:0]
R330
(014Ah)
Output
async
clock
15 OPCLK_ASYNC_
ENA
7:3 OPCLK_ASYNC_
DIV [4:0]
2:0 OPCLK_ASYNC_
SEL [2:0]
R338
(0152h)
Rate
Estimator
1
4 TRIG_ON_STAR
TUP
3:1 LRCLK_SRC
[2:0]
0 RATE_EST_ENA
R339
(0153h)
Rate
Estimator
2
4:0 SAMPLE_RATE_
DETECT_A [4:0]
DEFAULT
DESCRIPTION
000
OPCLK Source Frequency
000 = 6.144MHz (5.6448MHz)
001 = 12.288MHz (11.2896MHz)
010 = 24.576MHz (22.5792MHz)
011 = 49.152MHz (45.1584MHz)
All other codes are Reserved
The frequencies in brackets apply for
44.1kHz-related SYSCLK rates only (ie.
SAMPLE_RATE_n = 01XXX).
The OPCLK Source Frequency must be
less than or equal to the SYSCLK
frequency.
0
OPCLK_ASYNC Enable
0 = Disabled
1 = Enabled
00h
OPCLK_ASYNC Divider
00h = Divide by 1
01h = Divide by 1
02h = Divide by 2
03h = Divide by 3
…
1Fh = Divide by 31
000
OPCLK_ASYNC Source Frequency
000 = 6.144MHz (5.6448MHz)
001 = 12.288MHz (11.2896MHz)
010 = 24.576MHz (22.5792MHz)
011 = 49.152MHz (45.1584MHz)
All other codes are Reserved
The frequencies in brackets apply for
44.1kHz-related ASYNCCLK rates only
(ie. ASYNC_SAMPLE_RATE_n =
01XXX).
The OPCLK_ASYNC Source Frequency
must be less than or equal to the
ASYNCCLK frequency.
0
Automatic Sample Rate Detection Start-
Up select
0 = Do not trigger Write Sequence on
initial detection
1 = Always trigger the Write Sequencer on
sample rate detection
000
Automatic Sample Rate Detection source
000 = AIF1RXLRCLK
001 = AIF1TXLRCLK
010 = AIF2RXLRCLK
011 = AIF2TXLRCLK
100 = AIF3RXLRCLK
101 = AIF3TXLRCLK
110 = Reserved
111 = Reserved
0
Automatic Sample Rate Detection control
0 = Disabled
1 = Enabled
00h
Automatic Detection Sample Rate A
(Up to four different sample rates can be
configured for automatic detection.)
Register coding is same as
SAMPLE_RATE_n.
Rev 4.0