WM8281 Datasheet, PDF (264/392 Pages) Cirrus Logic – Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation

264
WM8281
There are some restrictions to be observed regarding the automatic sample rate detection, as noted
below:
 The same sample rate must not be selected on more than one of the
SAMPLE_RATE_DETECT_n registers.
 Sample rates 192kHz and 176.4kHz must not be selected concurrently.
 Sample rates 96kHz and 88.2kHz must not be selected concurrently.
The control registers associated with the automatic sample rate detection function are described in
Table 101.
SYSCLK AND ASYNCCLK CONTROL
The SYSCLK and ASYNCCLK clocks may be provided directly from external inputs (MCLK, or slave
mode BCLK inputs). Alternatively, the SYSCLK and ASYNCCLK clocks can be derived using the
integrated FLL(s), with MCLK, BCLK, LRCLK or SLIMCLK as a reference.
The required SYSCLK frequency is dependent on the SAMPLE_RATE_n registers. Table 99
illustrates the valid SYSCLK frequencies for every supported sample rate.
The SYSCLK_FREQ and SYSCLK_FRAC registers are used to identify the applicable SYSCLK
frequency. It is recommended that the highest possible SYSCLK frequency is selected.
The chosen SYSCLK frequency must be valid for all of the SAMPLE_RATE_n registers. It follows that
all of the SAMPLE_RATE_n registers must select numerically-related values, ie. all from the same cell
as represented in Table 99.
Sample Rate SAMPLE_RATE_n
SYSCLK
Frequency
SYSCLK_FREQ SYSCLK_FRAC
12kHz
01h
24kHz
02h
6.144MHz,
000,
48kHz
03h
12.288MHz,
001,
96kHz
04h
24.576MHz,
010,
192kHz
05h
49.152MHz,
011,
73.728MHz,
100,
0
4kHz
10h
98.304MHz,
101,
8kHz
11h
or
or
16kHz
12h
147.456MHz
110
32kHz
13h
5.6448MHz,
000,
11.025kHz
09h
11.2896MHz,
001,
22.05kHz
0Ah
22.5792MHz,
010,
44.1kHz
0Bh
45.1584MHz,
011,
67.7376MHz,
100,
1
88.2kHz
0Ch
90.3168MHz,
101,
176.4kHz
0Dh
or
or
135.4752MHz
110
Note that each of the SAMPLE_RATE_n registers must select a sample rate value from the same
group in the two lists above.
Table 99 SYSCLK Frequency Selection
The required ASYNCCLK frequency is dependent on the ASYNC_SAMPLE_RATE_n registers. Table
100 illustrates the valid ASYNCCLK frequencies for every supported sample rate.
The ASYNC_CLK_FREQ register is used to identify the applicable ASYNCCLK frequency. It is
recommended that the highest possible ASYNCCLK frequency is selected.
Note that, if all the sample rates in the system are synchronised to SYSCLK, then the ASYNCCLK
may not be required at all. In this case, the ASYNCCLK should be disabled (see Table 101), and the
associated register values are not important.
Rev 4.0